Search

Lindsay M Maguire

Examiner (ID: 2393, Phone: (571)272-6039 , Office: P/3693 )

Most Active Art Unit
3693
Art Unit(s)
3693, 3695, 3692, 3619, 3634
Total Applications
797
Issued Applications
386
Pending Applications
54
Abandoned Applications
319

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3817815 [patent_doc_number] => 05811991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Logic circuit and semiconductor device using it' [patent_app_type] => 1 [patent_app_number] => 8/613086 [patent_app_country] => US [patent_app_date] => 1996-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5447 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811991.pdf [firstpage_image] =>[orig_patent_app_number] => 613086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/613086
Logic circuit and semiconductor device using it Mar 7, 1996 Issued
Array ( [id] => 3703372 [patent_doc_number] => 05677637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Logic device using single electron coulomb blockade techniques' [patent_app_type] => 1 [patent_app_number] => 8/606835 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 73 [patent_no_of_words] => 12096 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677637.pdf [firstpage_image] =>[orig_patent_app_number] => 606835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/606835
Logic device using single electron coulomb blockade techniques Feb 26, 1996 Issued
Array ( [id] => 3956588 [patent_doc_number] => 05955896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Input buffer using a differential amplifier' [patent_app_type] => 1 [patent_app_number] => 8/606852 [patent_app_country] => US [patent_app_date] => 1996-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 7297 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/955/05955896.pdf [firstpage_image] =>[orig_patent_app_number] => 606852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/606852
Input buffer using a differential amplifier Feb 25, 1996 Issued
Array ( [id] => 3847503 [patent_doc_number] => 05744980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Flexible, high-performance static RAM architecture for field-programmable gate arrays' [patent_app_type] => 1 [patent_app_number] => 8/603597 [patent_app_country] => US [patent_app_date] => 1996-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5923 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744980.pdf [firstpage_image] =>[orig_patent_app_number] => 603597 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/603597
Flexible, high-performance static RAM architecture for field-programmable gate arrays Feb 15, 1996 Issued
Array ( [id] => 3663414 [patent_doc_number] => 05627481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Fast transmission line implemented with receiver, driver, terminator and IC arrangements' [patent_app_type] => 1 [patent_app_number] => 8/596724 [patent_app_country] => US [patent_app_date] => 1996-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 52 [patent_no_of_words] => 10292 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627481.pdf [firstpage_image] =>[orig_patent_app_number] => 596724 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/596724
Fast transmission line implemented with receiver, driver, terminator and IC arrangements Feb 4, 1996 Issued
08/596773 FAST TRANSMISSION LINE IMPLEMENTED WITH RECEIVER, DRIVER, TERMINATOR AND IC ARRANGEMENTS Feb 4, 1996 Abandoned
Array ( [id] => 3881400 [patent_doc_number] => 05764077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => '5 volt tolerant I/O buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/597889 [patent_app_country] => US [patent_app_date] => 1996-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4107 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 478 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764077.pdf [firstpage_image] =>[orig_patent_app_number] => 597889 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/597889
5 volt tolerant I/O buffer circuit Feb 4, 1996 Issued
Array ( [id] => 3703388 [patent_doc_number] => 05677638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'High speed tristate bus with multiplexers for selecting bus driver' [patent_app_type] => 1 [patent_app_number] => 8/595676 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3632 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677638.pdf [firstpage_image] =>[orig_patent_app_number] => 595676 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/595676
High speed tristate bus with multiplexers for selecting bus driver Feb 1, 1996 Issued
Array ( [id] => 3853864 [patent_doc_number] => 05719504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Semiconductor device having a scan path' [patent_app_type] => 1 [patent_app_number] => 8/591976 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 41 [patent_no_of_words] => 4165 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719504.pdf [firstpage_image] =>[orig_patent_app_number] => 591976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/591976
Semiconductor device having a scan path Jan 28, 1996 Issued
Array ( [id] => 4071598 [patent_doc_number] => 05867040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and reduce the voltage across any one transistor' [patent_app_type] => 1 [patent_app_number] => 8/593275 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6863 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867040.pdf [firstpage_image] =>[orig_patent_app_number] => 593275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/593275
Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and reduce the voltage across any one transistor Jan 28, 1996 Issued
Array ( [id] => 3761929 [patent_doc_number] => 05721497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Cold termination for a bus' [patent_app_type] => 1 [patent_app_number] => 8/589090 [patent_app_country] => US [patent_app_date] => 1996-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5088 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721497.pdf [firstpage_image] =>[orig_patent_app_number] => 589090 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/589090
Cold termination for a bus Jan 22, 1996 Issued
Array ( [id] => 3836832 [patent_doc_number] => 05760602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA' [patent_app_type] => 1 [patent_app_number] => 8/587687 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3995 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760602.pdf [firstpage_image] =>[orig_patent_app_number] => 587687 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/587687
Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA Jan 16, 1996 Issued
Array ( [id] => 3693690 [patent_doc_number] => 05691653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Product term based programmable logic array devices with reduced control memory requirements' [patent_app_type] => 1 [patent_app_number] => 8/586087 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2616 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691653.pdf [firstpage_image] =>[orig_patent_app_number] => 586087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/586087
Product term based programmable logic array devices with reduced control memory requirements Jan 15, 1996 Issued
Array ( [id] => 4005256 [patent_doc_number] => 05986474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Data line bias circuit' [patent_app_type] => 1 [patent_app_number] => 8/585994 [patent_app_country] => US [patent_app_date] => 1996-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3957 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986474.pdf [firstpage_image] =>[orig_patent_app_number] => 585994 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/585994
Data line bias circuit Jan 11, 1996 Issued
Array ( [id] => 3859577 [patent_doc_number] => 05767697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Low-voltage output circuit for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/584487 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5766 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767697.pdf [firstpage_image] =>[orig_patent_app_number] => 584487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/584487
Low-voltage output circuit for semiconductor device Jan 10, 1996 Issued
Array ( [id] => 3893253 [patent_doc_number] => 05894228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Tristate structures for programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/587875 [patent_app_country] => US [patent_app_date] => 1996-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7790 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894228.pdf [firstpage_image] =>[orig_patent_app_number] => 587875 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/587875
Tristate structures for programmable logic devices Jan 9, 1996 Issued
Array ( [id] => 3884797 [patent_doc_number] => 05748010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Logic signal level translation apparatus having very low dropout with respect to the powering rails' [patent_app_type] => 1 [patent_app_number] => 8/582227 [patent_app_country] => US [patent_app_date] => 1996-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4307 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748010.pdf [firstpage_image] =>[orig_patent_app_number] => 582227 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/582227
Logic signal level translation apparatus having very low dropout with respect to the powering rails Jan 2, 1996 Issued
90/004080 CONTROLLABLE BUS TERMINATOR Dec 19, 1995 Issued
90/004074 CONTROLLABLE BUS TERMINATOR WITH VOLTAGE REGULATION Dec 19, 1995 Issued
Array ( [id] => 3595429 [patent_doc_number] => 05585743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'ECL-CMOS level conversion circuit' [patent_app_type] => 1 [patent_app_number] => 8/570830 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3205 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585743.pdf [firstpage_image] =>[orig_patent_app_number] => 570830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/570830
ECL-CMOS level conversion circuit Dec 11, 1995 Issued
Menu