Application number | Title of the application | Filing Date | Status |
---|
Array
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[patent_title] => 'Device and method for programming high impedance states upon select input/output pads'
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Array
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[patent_doc_number] => 05818259
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[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Low voltage logic circuit'
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Array
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[patent_doc_number] => 05801550
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[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Output circuit device preventing overshoot and undershoot'
[patent_app_type] => 1
[patent_app_number] => 8/564499
[patent_app_country] => US
[patent_app_date] => 1995-11-29
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Array
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[patent_doc_number] => 05694054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Integrated drivers for flat panel displays employing chalcogenide logic elements'
[patent_app_type] => 1
[patent_app_number] => 8/565187
[patent_app_country] => US
[patent_app_date] => 1995-11-28
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Array
(
[id] => 3767106
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[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Decoder with reduced architecture'
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[patent_app_number] => 8/560090
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[firstpage_image] =>[orig_patent_app_number] => 560090
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/560090 | Decoder with reduced architecture | Nov 16, 1995 | Issued |
Array
(
[id] => 3734304
[patent_doc_number] => 05670899
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Logic circuit controlled by a plurality of clock signals'
[patent_app_type] => 1
[patent_app_number] => 8/556199
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Array
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[id] => 3694178
[patent_doc_number] => 05663660
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[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Device for matching a line interface of a station linked to a multiplexed-information transmission network'
[patent_app_type] => 1
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Array
(
[id] => 3666671
[patent_doc_number] => 05656950
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Interconnect lines including tri-directional buffer circuits'
[patent_app_type] => 1
[patent_app_number] => 8/548791
[patent_app_country] => US
[patent_app_date] => 1995-10-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/656/05656950.pdf
[firstpage_image] =>[orig_patent_app_number] => 548791
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/548791 | Interconnect lines including tri-directional buffer circuits | Oct 25, 1995 | Issued |
08/548498 | SYSTEM AND METHOD FOR ISOLATION OF VARYING-POWER BACKED MEMORY CONTROLLER INPUTS | Oct 25, 1995 | Abandoned |
08/547966 | INTEGRATED CIRCUITS FOR LOW POWER DISSIPATION IN SIGNALING BETWEEN DIFFERENT-VOLTAGE ON CHIP REGIONS | Oct 24, 1995 | Abandoned |
Array
(
[id] => 3734249
[patent_doc_number] => 05670895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Routing connections for programmable logic array integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/545084
[patent_app_country] => US
[patent_app_date] => 1995-10-19
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[pdf_file] => patents/05/670/05670895.pdf
[firstpage_image] =>[orig_patent_app_number] => 545084
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/545084 | Routing connections for programmable logic array integrated circuits | Oct 18, 1995 | Issued |
Array
(
[id] => 3838927
[patent_doc_number] => 05815004
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Multi-buffered configurable logic block output lines in a field programmable gate array'
[patent_app_type] => 1
[patent_app_number] => 8/543591
[patent_app_country] => US
[patent_app_date] => 1995-10-16
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Array
(
[id] => 3837766
[patent_doc_number] => 05712579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Deskewed clock distribution network with edge clock'
[patent_app_type] => 1
[patent_app_number] => 8/543693
[patent_app_country] => US
[patent_app_date] => 1995-10-16
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Array
(
[id] => 3817704
[patent_doc_number] => 05811984
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Current mode I/O for digital circuits'
[patent_app_type] => 1
[patent_app_number] => 8/539581
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[patent_app_date] => 1995-10-05
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[firstpage_image] =>[orig_patent_app_number] => 539581
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/539581 | Current mode I/O for digital circuits | Oct 4, 1995 | Issued |
08/539423 | DIALER WITH INTERNAL OPTION SELECT CIRCUIT PROGRAMMED WITH EXTERNALLY HARDWIRED ADDRESS | Oct 4, 1995 | Abandoned |
Array
(
[id] => 3666927
[patent_doc_number] => 05648732
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[patent_kind] => NA
[patent_issue_date] => 1997-07-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/539289 | Field programmable pipeline array | Oct 3, 1995 | Issued |
Array
(
[id] => 3784575
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[patent_kind] => NA
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/536287 | Method and circuit for using a function generator of a programmable logic device to implement carry logic functions | Sep 28, 1995 | Issued |
Array
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[id] => 3831630
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[patent_kind] => NA
[patent_issue_date] => 1998-03-24
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[patent_app_type] => 1
[patent_app_number] => 8/535876
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/534487 | High speed reduced area multiplexer | Sep 26, 1995 | Issued |