Search

Lindsay M Maguire

Examiner (ID: 2393, Phone: (571)272-6039 , Office: P/3693 )

Most Active Art Unit
3693
Art Unit(s)
3693, 3695, 3692, 3619, 3634
Total Applications
797
Issued Applications
386
Pending Applications
54
Abandoned Applications
319

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3737406 [patent_doc_number] => 05666071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Device and method for programming high impedance states upon select input/output pads' [patent_app_type] => 1 [patent_app_number] => 8/565684 [patent_app_country] => US [patent_app_date] => 1995-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6237 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666071.pdf [firstpage_image] =>[orig_patent_app_number] => 565684 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565684
Device and method for programming high impedance states upon select input/output pads Nov 30, 1995 Issued
Array ( [id] => 3784508 [patent_doc_number] => 05818259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Low voltage logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/565695 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2776 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818259.pdf [firstpage_image] =>[orig_patent_app_number] => 565695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565695
Low voltage logic circuit Nov 29, 1995 Issued
Array ( [id] => 3749903 [patent_doc_number] => 05801550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Output circuit device preventing overshoot and undershoot' [patent_app_type] => 1 [patent_app_number] => 8/564499 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8125 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801550.pdf [firstpage_image] =>[orig_patent_app_number] => 564499 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/564499
Output circuit device preventing overshoot and undershoot Nov 28, 1995 Issued
Array ( [id] => 3737391 [patent_doc_number] => 05694054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Integrated drivers for flat panel displays employing chalcogenide logic elements' [patent_app_type] => 1 [patent_app_number] => 8/565187 [patent_app_country] => US [patent_app_date] => 1995-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7533 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694054.pdf [firstpage_image] =>[orig_patent_app_number] => 565187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565187
Integrated drivers for flat panel displays employing chalcogenide logic elements Nov 27, 1995 Issued
Array ( [id] => 3767106 [patent_doc_number] => 05742187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Decoder with reduced architecture' [patent_app_type] => 1 [patent_app_number] => 8/560090 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3872 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742187.pdf [firstpage_image] =>[orig_patent_app_number] => 560090 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560090
Decoder with reduced architecture Nov 16, 1995 Issued
Array ( [id] => 3734304 [patent_doc_number] => 05670899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Logic circuit controlled by a plurality of clock signals' [patent_app_type] => 1 [patent_app_number] => 8/556199 [patent_app_country] => US [patent_app_date] => 1995-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4428 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670899.pdf [firstpage_image] =>[orig_patent_app_number] => 556199 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/556199
Logic circuit controlled by a plurality of clock signals Nov 8, 1995 Issued
Array ( [id] => 3694178 [patent_doc_number] => 05663660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Device for matching a line interface of a station linked to a multiplexed-information transmission network' [patent_app_type] => 1 [patent_app_number] => 8/556096 [patent_app_country] => US [patent_app_date] => 1995-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1515 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663660.pdf [firstpage_image] =>[orig_patent_app_number] => 556096 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/556096
Device for matching a line interface of a station linked to a multiplexed-information transmission network Nov 8, 1995 Issued
Array ( [id] => 3666671 [patent_doc_number] => 05656950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Interconnect lines including tri-directional buffer circuits' [patent_app_type] => 1 [patent_app_number] => 8/548791 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3378 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656950.pdf [firstpage_image] =>[orig_patent_app_number] => 548791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548791
Interconnect lines including tri-directional buffer circuits Oct 25, 1995 Issued
08/548498 SYSTEM AND METHOD FOR ISOLATION OF VARYING-POWER BACKED MEMORY CONTROLLER INPUTS Oct 25, 1995 Abandoned
08/547966 INTEGRATED CIRCUITS FOR LOW POWER DISSIPATION IN SIGNALING BETWEEN DIFFERENT-VOLTAGE ON CHIP REGIONS Oct 24, 1995 Abandoned
Array ( [id] => 3734249 [patent_doc_number] => 05670895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Routing connections for programmable logic array integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/545084 [patent_app_country] => US [patent_app_date] => 1995-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11931 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670895.pdf [firstpage_image] =>[orig_patent_app_number] => 545084 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/545084
Routing connections for programmable logic array integrated circuits Oct 18, 1995 Issued
Array ( [id] => 3838927 [patent_doc_number] => 05815004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Multi-buffered configurable logic block output lines in a field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/543591 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2968 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815004.pdf [firstpage_image] =>[orig_patent_app_number] => 543591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543591
Multi-buffered configurable logic block output lines in a field programmable gate array Oct 15, 1995 Issued
Array ( [id] => 3837766 [patent_doc_number] => 05712579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Deskewed clock distribution network with edge clock' [patent_app_type] => 1 [patent_app_number] => 8/543693 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7098 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712579.pdf [firstpage_image] =>[orig_patent_app_number] => 543693 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543693
Deskewed clock distribution network with edge clock Oct 15, 1995 Issued
Array ( [id] => 3817704 [patent_doc_number] => 05811984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Current mode I/O for digital circuits' [patent_app_type] => 1 [patent_app_number] => 8/539581 [patent_app_country] => US [patent_app_date] => 1995-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5855 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811984.pdf [firstpage_image] =>[orig_patent_app_number] => 539581 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539581
Current mode I/O for digital circuits Oct 4, 1995 Issued
08/539423 DIALER WITH INTERNAL OPTION SELECT CIRCUIT PROGRAMMED WITH EXTERNALLY HARDWIRED ADDRESS Oct 4, 1995 Abandoned
Array ( [id] => 3666927 [patent_doc_number] => 05648732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Field programmable pipeline array' [patent_app_type] => 1 [patent_app_number] => 8/539289 [patent_app_country] => US [patent_app_date] => 1995-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5693 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648732.pdf [firstpage_image] =>[orig_patent_app_number] => 539289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539289
Field programmable pipeline array Oct 3, 1995 Issued
Array ( [id] => 3784575 [patent_doc_number] => 05818263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method and apparatus for locating and improving race conditions in VLSI integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/536435 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2470 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818263.pdf [firstpage_image] =>[orig_patent_app_number] => 536435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536435
Method and apparatus for locating and improving race conditions in VLSI integrated circuits Sep 28, 1995 Issued
Array ( [id] => 3784448 [patent_doc_number] => 05818255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method and circuit for using a function generator of a programmable logic device to implement carry logic functions' [patent_app_type] => 1 [patent_app_number] => 8/536287 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3989 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818255.pdf [firstpage_image] =>[orig_patent_app_number] => 536287 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536287
Method and circuit for using a function generator of a programmable logic device to implement carry logic functions Sep 28, 1995 Issued
Array ( [id] => 3831630 [patent_doc_number] => 05731714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Off-chip driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/535876 [patent_app_country] => US [patent_app_date] => 1995-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3963 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731714.pdf [firstpage_image] =>[orig_patent_app_number] => 535876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/535876
Off-chip driver circuit Sep 27, 1995 Issued
Array ( [id] => 3669969 [patent_doc_number] => 05598114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'High speed reduced area multiplexer' [patent_app_type] => 1 [patent_app_number] => 8/534487 [patent_app_country] => US [patent_app_date] => 1995-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3667 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598114.pdf [firstpage_image] =>[orig_patent_app_number] => 534487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534487
High speed reduced area multiplexer Sep 26, 1995 Issued
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