Search

Neil S Levy

Examiner (ID: 11154)

Most Active Art Unit
1615
Art Unit(s)
1617, 1615, 1502, 1616
Total Applications
2341
Issued Applications
1326
Pending Applications
298
Abandoned Applications
664

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4216117 [patent_doc_number] => 06014763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'At-speed scan testing' [patent_app_type] => 1 [patent_app_number] => 9/007670 [patent_app_country] => US [patent_app_date] => 1998-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3393 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014763.pdf [firstpage_image] =>[orig_patent_app_number] => 007670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007670
At-speed scan testing Jan 14, 1998 Issued
Array ( [id] => 4172051 [patent_doc_number] => 06125465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Isolation/removal of faults during LBIST testing' [patent_app_type] => 1 [patent_app_number] => 9/004873 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1252 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125465.pdf [firstpage_image] =>[orig_patent_app_number] => 004873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004873
Isolation/removal of faults during LBIST testing Jan 8, 1998 Issued
Array ( [id] => 4124604 [patent_doc_number] => 06101619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method for improving access performance on track with re-allocation sector in a hard disk drive' [patent_app_type] => 1 [patent_app_number] => 9/001471 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4143 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101619.pdf [firstpage_image] =>[orig_patent_app_number] => 001471 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001471
Method for improving access performance on track with re-allocation sector in a hard disk drive Dec 30, 1997 Issued
Array ( [id] => 3968195 [patent_doc_number] => 05983381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Partitioning and reordering methods for static test sequence compaction of sequential circuits' [patent_app_type] => 1 [patent_app_number] => 9/001542 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4806 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983381.pdf [firstpage_image] =>[orig_patent_app_number] => 001542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001542
Partitioning and reordering methods for static test sequence compaction of sequential circuits Dec 30, 1997 Issued
Array ( [id] => 4258360 [patent_doc_number] => 06145106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'State relaxation based subsequence removal method for fast static compaction in sequential circuits' [patent_app_type] => 1 [patent_app_number] => 9/001543 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5181 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145106.pdf [firstpage_image] =>[orig_patent_app_number] => 001543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001543
State relaxation based subsequence removal method for fast static compaction in sequential circuits Dec 30, 1997 Issued
Array ( [id] => 4224651 [patent_doc_number] => 06079039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Test circuit and test method for testing semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 8/997720 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4331 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079039.pdf [firstpage_image] =>[orig_patent_app_number] => 997720 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997720
Test circuit and test method for testing semiconductor chip Dec 22, 1997 Issued
Array ( [id] => 4255812 [patent_doc_number] => 06119254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Hardware tracing/logging for highly integrated embedded controller device' [patent_app_type] => 1 [patent_app_number] => 8/997130 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7582 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119254.pdf [firstpage_image] =>[orig_patent_app_number] => 997130 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997130
Hardware tracing/logging for highly integrated embedded controller device Dec 22, 1997 Issued
Array ( [id] => 4058211 [patent_doc_number] => 05996100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'System and method for the injection and cancellation of a bias voltage in an attenuated circuit' [patent_app_type] => 1 [patent_app_number] => 8/995302 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3442 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996100.pdf [firstpage_image] =>[orig_patent_app_number] => 995302 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995302
System and method for the injection and cancellation of a bias voltage in an attenuated circuit Dec 21, 1997 Issued
08/992941 PARALLEL TEST METHOD Dec 17, 1997 Abandoned
Array ( [id] => 3989738 [patent_doc_number] => 05917833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Testing apparatus for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/988471 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2876 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917833.pdf [firstpage_image] =>[orig_patent_app_number] => 988471 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988471
Testing apparatus for semiconductor device Dec 9, 1997 Issued
Array ( [id] => 3940820 [patent_doc_number] => 05878055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method and apparatus for verifying a single phase clocking system including testing for latch early mode' [patent_app_type] => 1 [patent_app_number] => 8/987702 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4181 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878055.pdf [firstpage_image] =>[orig_patent_app_number] => 987702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987702
Method and apparatus for verifying a single phase clocking system including testing for latch early mode Dec 8, 1997 Issued
Array ( [id] => 3945578 [patent_doc_number] => 05935265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Scan path circuit permitting transition between first and second sets of check data' [patent_app_type] => 1 [patent_app_number] => 8/982882 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4313 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935265.pdf [firstpage_image] =>[orig_patent_app_number] => 982882 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982882
Scan path circuit permitting transition between first and second sets of check data Dec 1, 1997 Issued
Array ( [id] => 4161302 [patent_doc_number] => 06061817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method and apparatus for generating test pattern for sequence detection' [patent_app_type] => 1 [patent_app_number] => 8/982730 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9433 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061817.pdf [firstpage_image] =>[orig_patent_app_number] => 982730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982730
Method and apparatus for generating test pattern for sequence detection Dec 1, 1997 Issued
Array ( [id] => 4226263 [patent_doc_number] => 06029262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Graphical editor for defining memory test sequences' [patent_app_type] => 1 [patent_app_number] => 8/978083 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5817 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029262.pdf [firstpage_image] =>[orig_patent_app_number] => 978083 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978083
Graphical editor for defining memory test sequences Nov 24, 1997 Issued
Array ( [id] => 4035465 [patent_doc_number] => 05926486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Automated system for determining the dynamic thresholds of digital logic devices' [patent_app_type] => 1 [patent_app_number] => 8/978462 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3717 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926486.pdf [firstpage_image] =>[orig_patent_app_number] => 978462 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978462
Automated system for determining the dynamic thresholds of digital logic devices Nov 24, 1997 Issued
Array ( [id] => 3916525 [patent_doc_number] => 05898703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Device and method for testing integrated circuit including bi-directional test pin for receiving control data and outputting observation data' [patent_app_type] => 1 [patent_app_number] => 8/976572 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9807 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898703.pdf [firstpage_image] =>[orig_patent_app_number] => 976572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976572
Device and method for testing integrated circuit including bi-directional test pin for receiving control data and outputting observation data Nov 23, 1997 Issued
Array ( [id] => 3968141 [patent_doc_number] => 05983377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'System and circuit for ASIC pin fault testing' [patent_app_type] => 1 [patent_app_number] => 8/972352 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9809 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983377.pdf [firstpage_image] =>[orig_patent_app_number] => 972352 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972352
System and circuit for ASIC pin fault testing Nov 16, 1997 Issued
Array ( [id] => 3974337 [patent_doc_number] => 05978946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Methods and apparatus for system testing of processors and computers using signature analysis' [patent_app_type] => 1 [patent_app_number] => 8/962160 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5599 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978946.pdf [firstpage_image] =>[orig_patent_app_number] => 962160 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962160
Methods and apparatus for system testing of processors and computers using signature analysis Oct 30, 1997 Issued
Array ( [id] => 3971665 [patent_doc_number] => 06000050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method for minimizing ground bounce during DC parametric tests using boundary scan register' [patent_app_type] => 1 [patent_app_number] => 8/956872 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11438 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000050.pdf [firstpage_image] =>[orig_patent_app_number] => 956872 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956872
Method for minimizing ground bounce during DC parametric tests using boundary scan register Oct 22, 1997 Issued
Array ( [id] => 4193270 [patent_doc_number] => 06141780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Fabrication process acceptance tester and fabrication process using a maintenance region of a disk' [patent_app_type] => 1 [patent_app_number] => 8/951153 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2334 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141780.pdf [firstpage_image] =>[orig_patent_app_number] => 951153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/951153
Fabrication process acceptance tester and fabrication process using a maintenance region of a disk Oct 14, 1997 Issued
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