Search

Neil S Levy

Examiner (ID: 11154)

Most Active Art Unit
1615
Art Unit(s)
1617, 1615, 1502, 1616
Total Applications
2341
Issued Applications
1326
Pending Applications
298
Abandoned Applications
664

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3948518 [patent_doc_number] => 05940413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method for detecting operational errors in a tester for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/081030 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 3 [patent_no_of_words] => 2816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940413.pdf [firstpage_image] =>[orig_patent_app_number] => 081030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081030
Method for detecting operational errors in a tester for semiconductor devices May 18, 1998 Issued
Array ( [id] => 4066239 [patent_doc_number] => 05970073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Test pattern generator circuit for IC testing equipment' [patent_app_type] => 1 [patent_app_number] => 9/080451 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4277 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970073.pdf [firstpage_image] =>[orig_patent_app_number] => 080451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080451
Test pattern generator circuit for IC testing equipment May 17, 1998 Issued
Array ( [id] => 4426770 [patent_doc_number] => 06178534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'System and method for using LBIST to find critical paths in functional logic' [patent_app_type] => 1 [patent_app_number] => 9/076221 [patent_app_country] => US [patent_app_date] => 1998-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 8 [patent_no_of_words] => 6482 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178534.pdf [firstpage_image] =>[orig_patent_app_number] => 076221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076221
System and method for using LBIST to find critical paths in functional logic May 10, 1998 Issued
Array ( [id] => 4239857 [patent_doc_number] => 06088824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Test pattern generating apparatus, communication device and simulator' [patent_app_type] => 1 [patent_app_number] => 9/071891 [patent_app_country] => US [patent_app_date] => 1998-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4888 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088824.pdf [firstpage_image] =>[orig_patent_app_number] => 071891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071891
Test pattern generating apparatus, communication device and simulator May 4, 1998 Issued
Array ( [id] => 4153334 [patent_doc_number] => 06148426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Apparatus and method for generating addresses in a SRAM built-in self test circuit using a single-direction counter' [patent_app_type] => 1 [patent_app_number] => 9/067671 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148426.pdf [firstpage_image] =>[orig_patent_app_number] => 067671 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067671
Apparatus and method for generating addresses in a SRAM built-in self test circuit using a single-direction counter Apr 27, 1998 Issued
Array ( [id] => 4161259 [patent_doc_number] => 06061814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers' [patent_app_type] => 1 [patent_app_number] => 9/063801 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4071 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061814.pdf [firstpage_image] =>[orig_patent_app_number] => 063801 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063801
Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers Apr 20, 1998 Issued
Array ( [id] => 3974399 [patent_doc_number] => 05978949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Failure analysis device for IC tester and memory device measuring device for IC tester' [patent_app_type] => 1 [patent_app_number] => 9/059282 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3939 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978949.pdf [firstpage_image] =>[orig_patent_app_number] => 059282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059282
Failure analysis device for IC tester and memory device measuring device for IC tester Apr 13, 1998 Issued
Array ( [id] => 4255738 [patent_doc_number] => 06119249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Memory devices operable in both a normal and a test mode and methods for testing same' [patent_app_type] => 1 [patent_app_number] => 9/049952 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5887 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119249.pdf [firstpage_image] =>[orig_patent_app_number] => 049952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049952
Memory devices operable in both a normal and a test mode and methods for testing same Mar 26, 1998 Issued
Array ( [id] => 4179817 [patent_doc_number] => 06115833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Semiconductor memory testing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/040724 [patent_app_country] => US [patent_app_date] => 1998-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5169 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115833.pdf [firstpage_image] =>[orig_patent_app_number] => 040724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/040724
Semiconductor memory testing apparatus Mar 17, 1998 Issued
Array ( [id] => 4149134 [patent_doc_number] => 06016560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Semiconductor memory, memory device, and memory card' [patent_app_type] => 1 [patent_app_number] => 8/981094 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 68 [patent_no_of_words] => 22305 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016560.pdf [firstpage_image] =>[orig_patent_app_number] => 981094 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/981094
Semiconductor memory, memory device, and memory card Mar 16, 1998 Issued
Array ( [id] => 4313046 [patent_doc_number] => 06237124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Methods for errors checking the configuration SRAM and user assignable SRAM data in a field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 9/039924 [patent_app_country] => US [patent_app_date] => 1998-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6360 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237124.pdf [firstpage_image] =>[orig_patent_app_number] => 039924 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/039924
Methods for errors checking the configuration SRAM and user assignable SRAM data in a field programmable gate array Mar 15, 1998 Issued
Array ( [id] => 4195841 [patent_doc_number] => 06085350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Single event upset tolerant system and method' [patent_app_type] => 1 [patent_app_number] => 9/034282 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2910 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085350.pdf [firstpage_image] =>[orig_patent_app_number] => 034282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034282
Single event upset tolerant system and method Mar 3, 1998 Issued
Array ( [id] => 4026466 [patent_doc_number] => 05942000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Circuit and method for testing an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/032422 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/942/05942000.pdf [firstpage_image] =>[orig_patent_app_number] => 032422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032422
Circuit and method for testing an integrated circuit Feb 26, 1998 Issued
Array ( [id] => 4110841 [patent_doc_number] => 06134684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method and system for error detection in test units utilizing pseudo-random data' [patent_app_type] => 1 [patent_app_number] => 9/030972 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5846 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134684.pdf [firstpage_image] =>[orig_patent_app_number] => 030972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030972
Method and system for error detection in test units utilizing pseudo-random data Feb 24, 1998 Issued
Array ( [id] => 4195699 [patent_doc_number] => 06085341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Memory test mode for wordline resistive defects' [patent_app_type] => 1 [patent_app_number] => 9/030522 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 36 [patent_no_of_words] => 4349 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085341.pdf [firstpage_image] =>[orig_patent_app_number] => 030522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030522
Memory test mode for wordline resistive defects Feb 22, 1998 Issued
Array ( [id] => 4255850 [patent_doc_number] => 06119257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Semiconductor device testing apparatus capable of high speed test operation' [patent_app_type] => 1 [patent_app_number] => 9/027473 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6756 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119257.pdf [firstpage_image] =>[orig_patent_app_number] => 027473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027473
Semiconductor device testing apparatus capable of high speed test operation Feb 19, 1998 Issued
Array ( [id] => 4089236 [patent_doc_number] => 06070261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Multi-phase test point insertion for built-in self test of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/024962 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8419 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070261.pdf [firstpage_image] =>[orig_patent_app_number] => 024962 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024962
Multi-phase test point insertion for built-in self test of integrated circuits Feb 10, 1998 Issued
Array ( [id] => 4260925 [patent_doc_number] => 06092226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Fabrication of test logic for level sensitive scan on a circuit' [patent_app_type] => 1 [patent_app_number] => 9/021651 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6186 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092226.pdf [firstpage_image] =>[orig_patent_app_number] => 021651 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021651
Fabrication of test logic for level sensitive scan on a circuit Feb 9, 1998 Issued
Array ( [id] => 3969380 [patent_doc_number] => 05948115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Event phase modulator for integrated circuit tester' [patent_app_type] => 1 [patent_app_number] => 9/016532 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4299 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948115.pdf [firstpage_image] =>[orig_patent_app_number] => 016532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/016532
Event phase modulator for integrated circuit tester Jan 29, 1998 Issued
Array ( [id] => 3816557 [patent_doc_number] => 05854801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Pattern generation apparatus and method for SDRAM' [patent_app_type] => 1 [patent_app_number] => 8/894870 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2423 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854801.pdf [firstpage_image] =>[orig_patent_app_number] => 894870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/894870
Pattern generation apparatus and method for SDRAM Jan 19, 1998 Issued
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