Robert Scott Carrico
Examiner (ID: 15121, Phone: (571)270-5504 , Office: P/1727 )
Most Active Art Unit | 1727 |
Art Unit(s) | 1727 |
Total Applications | 625 |
Issued Applications | 350 |
Pending Applications | 72 |
Abandoned Applications | 203 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 11251982
[patent_doc_number] => 09477485
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-10-25
[patent_title] => 'Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets'
[patent_app_type] => utility
[patent_app_number] => 14/220194
[patent_app_country] => US
[patent_app_date] => 2014-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6348
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14220194
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/220194 | Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets | Mar 19, 2014 | Issued |
Array
(
[id] => 10383960
[patent_doc_number] => 20150268967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-24
[patent_title] => 'OPTIMIZING COMPUTER HARDWARE USAGE IN A COMPUTING SYSTEM THAT INCLUDES A PLURALITY OF POPULATED CENTRAL PROCESSING UNIT (\'CPU\') SOCKETS'
[patent_app_type] => utility
[patent_app_number] => 14/219286
[patent_app_country] => US
[patent_app_date] => 2014-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6323
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219286
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/219286 | Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets | Mar 18, 2014 | Issued |
Array
(
[id] => 11465664
[patent_doc_number] => 09582295
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-28
[patent_title] => 'Architectural mode configuration'
[patent_app_type] => utility
[patent_app_number] => 14/217840
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 29
[patent_no_of_words] => 24808
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217840
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/217840 | Architectural mode configuration | Mar 17, 2014 | Issued |
Array
(
[id] => 11465664
[patent_doc_number] => 09582295
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-28
[patent_title] => 'Architectural mode configuration'
[patent_app_type] => utility
[patent_app_number] => 14/217840
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 29
[patent_no_of_words] => 24808
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217840
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/217840 | Architectural mode configuration | Mar 17, 2014 | Issued |
Array
(
[id] => 11465664
[patent_doc_number] => 09582295
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-28
[patent_title] => 'Architectural mode configuration'
[patent_app_type] => utility
[patent_app_number] => 14/217840
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 29
[patent_no_of_words] => 24808
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217840
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/217840 | Architectural mode configuration | Mar 17, 2014 | Issued |
Array
(
[id] => 10383959
[patent_doc_number] => 20150268966
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-24
[patent_title] => 'COMMON BOOT SEQUENCE FOR CONTROL UTILITY ABLE TO BE INITIALIZED IN MULTIPLE ARCHITECTURES'
[patent_app_type] => utility
[patent_app_number] => 14/217800
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 26439
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217800
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/217800 | Common boot sequence for control utility able to be initialized in multiple architectures | Mar 17, 2014 | Issued |
Array
(
[id] => 11245191
[patent_doc_number] => 09471231
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-10-18
[patent_title] => 'Systems and methods for dynamic memory allocation of fault resistant memory (FRM)'
[patent_app_type] => utility
[patent_app_number] => 14/218393
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6225
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218393
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/218393 | Systems and methods for dynamic memory allocation of fault resistant memory (FRM) | Mar 17, 2014 | Issued |
Array
(
[id] => 10941569
[patent_doc_number] => 20140344590
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-20
[patent_title] => 'ELECTRONIC DEVICE AND POWER MANAGEMENT METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/217490
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 925
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217490
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/217490 | ELECTRONIC DEVICE AND POWER MANAGEMENT METHOD | Mar 17, 2014 | Abandoned |
Array
(
[id] => 11465664
[patent_doc_number] => 09582295
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-28
[patent_title] => 'Architectural mode configuration'
[patent_app_type] => utility
[patent_app_number] => 14/217840
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 29
[patent_no_of_words] => 24808
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217840
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/217840 | Architectural mode configuration | Mar 17, 2014 | Issued |
Array
(
[id] => 9745916
[patent_doc_number] => 20140281635
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'REDUCING POWER CONSUMPTION DURING IDLE STATE'
[patent_app_type] => utility
[patent_app_number] => 14/212135
[patent_app_country] => US
[patent_app_date] => 2014-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6298
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14212135
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/212135 | REDUCING POWER CONSUMPTION DURING IDLE STATE | Mar 13, 2014 | Abandoned |
Array
(
[id] => 9745915
[patent_doc_number] => 20140281634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'CONTROLLING POWER SUPPLY UNIT POWER CONSUMPTION DURING IDLE STATE'
[patent_app_type] => utility
[patent_app_number] => 14/211987
[patent_app_country] => US
[patent_app_date] => 2014-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6451
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14211987
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/211987 | CONTROLLING POWER SUPPLY UNIT POWER CONSUMPTION DURING IDLE STATE | Mar 13, 2014 | Abandoned |
Array
(
[id] => 11285282
[patent_doc_number] => 09501135
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-22
[patent_title] => 'Dynamic core selection for heterogeneous multi-core systems'
[patent_app_type] => utility
[patent_app_number] => 14/169955
[patent_app_country] => US
[patent_app_date] => 2014-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 12827
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169955
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/169955 | Dynamic core selection for heterogeneous multi-core systems | Jan 30, 2014 | Issued |
Array
(
[id] => 9637140
[patent_doc_number] => 20140215250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-31
[patent_title] => 'ELECTRONIC DEVICE AND POWER SAVING METHOD FOR ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/159547
[patent_app_country] => US
[patent_app_date] => 2014-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1272
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159547
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/159547 | ELECTRONIC DEVICE AND POWER SAVING METHOD FOR ELECTRONIC DEVICE | Jan 20, 2014 | Abandoned |
Array
(
[id] => 10320331
[patent_doc_number] => 20150205335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-23
[patent_title] => 'USER-PERSONALIZED WAKE POLICY BASED ON LEARNED USER BEHAVIOR'
[patent_app_type] => utility
[patent_app_number] => 14/160148
[patent_app_country] => US
[patent_app_date] => 2014-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4438
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160148
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/160148 | User-personalized wake policy based on learned user behavior | Jan 20, 2014 | Issued |
Array
(
[id] => 9673407
[patent_doc_number] => 20140237270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-21
[patent_title] => 'POWER SUPPLY CONTROL APPARATUS, POWER SUPPLY CONTROL SYSTEM AND POWER SUPPLY CONTROL METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/159694
[patent_app_country] => US
[patent_app_date] => 2014-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6746
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159694
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/159694 | POWER SUPPLY CONTROL APPARATUS, POWER SUPPLY CONTROL SYSTEM AND POWER SUPPLY CONTROL METHOD | Jan 20, 2014 | Abandoned |
Array
(
[id] => 10085132
[patent_doc_number] => 09122480
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-01
[patent_title] => 'Sleep wake event logging'
[patent_app_type] => utility
[patent_app_number] => 14/157104
[patent_app_country] => US
[patent_app_date] => 2014-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4705
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157104
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/157104 | Sleep wake event logging | Jan 15, 2014 | Issued |
Array
(
[id] => 11133166
[patent_doc_number] => 20160330142
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-10
[patent_title] => 'PACKET INSPECTION TO DETERMINE DESTINATION NODE'
[patent_app_type] => utility
[patent_app_number] => 15/110648
[patent_app_country] => US
[patent_app_date] => 2014-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3695
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15110648
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/110648 | Packet inspection to determine destination node | Jan 7, 2014 | Issued |
Array
(
[id] => 11452124
[patent_doc_number] => 09575768
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-02-21
[patent_title] => 'Loading boot code from multiple memories'
[patent_app_type] => utility
[patent_app_number] => 14/147087
[patent_app_country] => US
[patent_app_date] => 2014-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6301
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147087
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/147087 | Loading boot code from multiple memories | Jan 2, 2014 | Issued |
Array
(
[id] => 10228312
[patent_doc_number] => 20150113305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-23
[patent_title] => 'DATA STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/143889
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6751
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143889
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143889 | Data storage device | Dec 29, 2013 | Issued |
Array
(
[id] => 9571699
[patent_doc_number] => 20140189412
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-03
[patent_title] => 'TIME SEQUENCE CIRCUIT FOR POWER SUPPLY UNIT'
[patent_app_type] => utility
[patent_app_number] => 14/142916
[patent_app_country] => US
[patent_app_date] => 2013-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1190
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14142916
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/142916 | TIME SEQUENCE CIRCUIT FOR POWER SUPPLY UNIT | Dec 28, 2013 | Abandoned |