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Vu B Hang

Examiner (ID: 4126, Phone: (571)272-0582 , Office: P/2672 )

Most Active Art Unit
2672
Art Unit(s)
2625, 2671, 2654, 2672
Total Applications
753
Issued Applications
515
Pending Applications
46
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16782040 [patent_doc_number] => 20210119119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => TOP BUFFER LAYER FOR MAGNETIC TUNNEL JUNCTION APPLICATION [patent_app_type] => utility [patent_app_number] => 17/112484 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112484
Top buffer layer for magnetic tunnel junction application Dec 3, 2020 Issued
Array ( [id] => 16889127 [patent_doc_number] => 20210175324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SEMICONDUCTOR APPARATUS AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/110916 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110916 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110916
Semiconductor apparatus and device with semiconductor layer having crystal orientations that differ in Young's modulus and relative angle Dec 2, 2020 Issued
Array ( [id] => 18304598 [patent_doc_number] => 11626515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => High voltage semiconductor device including buried oxide layer and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/109153 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4660 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109153
High voltage semiconductor device including buried oxide layer and method for forming the same Dec 1, 2020 Issued
Array ( [id] => 18402240 [patent_doc_number] => 11664390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Flexible electronic device [patent_app_type] => utility [patent_app_number] => 17/109263 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6424 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109263
Flexible electronic device Dec 1, 2020 Issued
Array ( [id] => 16715895 [patent_doc_number] => 20210083042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR DEVICE HAVING CAPACITOR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/106409 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106409
Semiconductor device having capacitor and manufacturing method thereof Nov 29, 2020 Issued
Array ( [id] => 17971422 [patent_doc_number] => 11488971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Embedded memory with improved fill-in window [patent_app_type] => utility [patent_app_number] => 17/104686 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 9458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104686
Embedded memory with improved fill-in window Nov 24, 2020 Issued
Array ( [id] => 17862999 [patent_doc_number] => 11444161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Group III-V compound semiconductor substrate and group III-V compound semiconductor substrate with epitaxial layer [patent_app_type] => utility [patent_app_number] => 17/080165 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 22374 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080165
Group III-V compound semiconductor substrate and group III-V compound semiconductor substrate with epitaxial layer Oct 25, 2020 Issued
Array ( [id] => 16614113 [patent_doc_number] => 20210032766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => SEMICONDUCTOR DEVICE HAVING POROUS REGION EMBEDDED STRUCTURE AND METHOD OF MANUFACTURE THEREOF [patent_app_type] => utility [patent_app_number] => 17/075154 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075154
SEMICONDUCTOR DEVICE HAVING POROUS REGION EMBEDDED STRUCTURE AND METHOD OF MANUFACTURE THEREOF Oct 19, 2020 Pending
Array ( [id] => 16617284 [patent_doc_number] => 20210035937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => METHOD FOR FORMING PACKAGE STRUCTURE WITH A BARRIER LAYER [patent_app_type] => utility [patent_app_number] => 17/072798 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072798 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072798
Method for forming package structure with a barrier layer Oct 15, 2020 Issued
Array ( [id] => 17189121 [patent_doc_number] => 20210336006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => DIFFUSION BARRIER LAYER FOR SOURCE AND DRAIN STRUCTURES TO INCREASE TRANSISTOR PERFORMANCE [patent_app_type] => utility [patent_app_number] => 17/064811 [patent_app_country] => US [patent_app_date] => 2020-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/064811
Diffusion barrier layer for source and drain structures to increase transistor performance Oct 6, 2020 Issued
Array ( [id] => 17262653 [patent_doc_number] => 20210375638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR SUBSTRATE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/035750 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035750
SEMICONDUCTOR SUBSTRATE AND METHOD OF FORMING THE SAME Sep 28, 2020 Abandoned
Array ( [id] => 16578759 [patent_doc_number] => 20210013160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => CHIP PACKAGE WITH LID [patent_app_type] => utility [patent_app_number] => 17/034891 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034891
Chip package with lid Sep 27, 2020 Issued
Array ( [id] => 17574427 [patent_doc_number] => 11322702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Electrical devices having radiofrequency field effect transistors and the manufacture thereof [patent_app_type] => utility [patent_app_number] => 17/034933 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 8411 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034933
Electrical devices having radiofrequency field effect transistors and the manufacture thereof Sep 27, 2020 Issued
Array ( [id] => 17847988 [patent_doc_number] => 11437374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Semiconductor device and stacked semiconductor chips including through contacts [patent_app_type] => utility [patent_app_number] => 17/034296 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9819 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034296
Semiconductor device and stacked semiconductor chips including through contacts Sep 27, 2020 Issued
Array ( [id] => 18156139 [patent_doc_number] => 11569130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Fin field effect transistor (FinFET) device structure with dummy Fin structure [patent_app_type] => utility [patent_app_number] => 17/031023 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 6778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031023 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031023
Fin field effect transistor (FinFET) device structure with dummy Fin structure Sep 23, 2020 Issued
Array ( [id] => 16578905 [patent_doc_number] => 20210013306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/028042 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028042
Semiconductor device including a densified device isolation layer Sep 21, 2020 Issued
Array ( [id] => 17010864 [patent_doc_number] => 20210242025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SILICIDATION OF SOURCE/DRAIN REGION OF VERTICAL FIELD EFFECT TRANSISTOR (VFET) STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/026532 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026532
SILICIDATION OF SOURCE/DRAIN REGION OF VERTICAL FIELD EFFECT TRANSISTOR (VFET) STRUCTURE Sep 20, 2020 Abandoned
Array ( [id] => 17700167 [patent_doc_number] => 11373900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Damascene plug and tab patterning with photobuckets [patent_app_type] => utility [patent_app_number] => 17/025087 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 11055 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025087
Damascene plug and tab patterning with photobuckets Sep 17, 2020 Issued
Array ( [id] => 17787858 [patent_doc_number] => 11410994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Semiconductor devices with circuit and external dummy areas [patent_app_type] => utility [patent_app_number] => 17/024044 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024044 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/024044
Semiconductor devices with circuit and external dummy areas Sep 16, 2020 Issued
Array ( [id] => 16560419 [patent_doc_number] => 20210005568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Die Stack Arrangement Comprising a Die-Attach-Film Tape and Method for Producing Same [patent_app_type] => utility [patent_app_number] => 17/023986 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023986
Die stack arrangement comprising a die-attach-film tape and method for producing same Sep 16, 2020 Issued
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