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Vu B Hang

Examiner (ID: 4126, Phone: (571)272-0582 , Office: P/2672 )

Most Active Art Unit
2672
Art Unit(s)
2625, 2671, 2654, 2672
Total Applications
753
Issued Applications
515
Pending Applications
46
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18024540 [patent_doc_number] => 20220376039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LEAKAGE ESD MOSFET [patent_app_type] => utility [patent_app_number] => 17/326685 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326685
Low leakage ESD MOSFET May 20, 2021 Issued
Array ( [id] => 18507544 [patent_doc_number] => 11705371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Semiconductor devices having merged source/drain features and methods of fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/308552 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 51 [patent_no_of_words] => 15077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/308552
Semiconductor devices having merged source/drain features and methods of fabrication thereof May 4, 2021 Issued
Array ( [id] => 18236131 [patent_doc_number] => 11600699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Semiconductor device structure integrating air gaps and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/308258 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 41 [patent_no_of_words] => 10035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/308258
Semiconductor device structure integrating air gaps and methods of forming the same May 4, 2021 Issued
Array ( [id] => 17174430 [patent_doc_number] => 20210328101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => NANO-PHOTONICS REFLECTOR FOR LED EMITTERS [patent_app_type] => utility [patent_app_number] => 17/246398 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246398
Nano-photonics reflector for LED emitters Apr 29, 2021 Issued
Array ( [id] => 18088784 [patent_doc_number] => 11538923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Method for etching back hard mask layer on tops of dummy polysilicon gates in gate last process [patent_app_type] => utility [patent_app_number] => 17/242940 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 7180 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 451 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242940
Method for etching back hard mask layer on tops of dummy polysilicon gates in gate last process Apr 27, 2021 Issued
Array ( [id] => 17448573 [patent_doc_number] => 20220069078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/242823 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242823
Semiconductor device having an air gap between gate electrode and source/drain pattern Apr 27, 2021 Issued
Array ( [id] => 18520896 [patent_doc_number] => 11710791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Semiconductor structure with inversion layer between stress layer and protection layer and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/227682 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227682 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227682
Semiconductor structure with inversion layer between stress layer and protection layer and fabrication method thereof Apr 11, 2021 Issued
Array ( [id] => 17262708 [patent_doc_number] => 20210375693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SHALLOW TRENCH ISOLATION STRUCTURES HAVING UNIFORM STEP HEIGHTS [patent_app_type] => utility [patent_app_number] => 17/225249 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225249
Shallow trench isolation structures having uniform step heights Apr 7, 2021 Issued
Array ( [id] => 18357939 [patent_doc_number] => 11646346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Contact structure with air spacer for semiconductor device and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/225324 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 6035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225324
Contact structure with air spacer for semiconductor device and method for forming the same Apr 7, 2021 Issued
Array ( [id] => 16981652 [patent_doc_number] => 20210225889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/223276 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223276
Oxide semiconductor, thin film transistor, and display device Apr 5, 2021 Issued
Array ( [id] => 18205505 [patent_doc_number] => 11587910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Stacked semiconductor structure and method [patent_app_type] => utility [patent_app_number] => 17/223292 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 5446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223292
Stacked semiconductor structure and method Apr 5, 2021 Issued
Array ( [id] => 16981514 [patent_doc_number] => 20210225751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Semiconductor Device Having Via Sidewall Adhesion with Encapsulant [patent_app_type] => utility [patent_app_number] => 17/222118 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222118 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222118
Semiconductor device having via sidewall adhesion with encapsulant Apr 4, 2021 Issued
Array ( [id] => 16981800 [patent_doc_number] => 20210226037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Dummy Dielectric Fin Design for Parasitic Capacitance Reduction [patent_app_type] => utility [patent_app_number] => 17/222608 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222608 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222608
Dummy dielectric fin design for parasitic capacitance reduction Apr 4, 2021 Issued
Array ( [id] => 17772354 [patent_doc_number] => 11404305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-02 [patent_title] => Manufacturing method of isolation structures for semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/210494 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210494
Manufacturing method of isolation structures for semiconductor devices Mar 22, 2021 Issued
Array ( [id] => 17263129 [patent_doc_number] => 20210376114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/205120 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/205120
Fin field-effect transistor with void and method of forming the same Mar 17, 2021 Issued
Array ( [id] => 18983729 [patent_doc_number] => 11908919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Multi-gate devices with multi-layer inner spacers and fabrication methods thereof [patent_app_type] => utility [patent_app_number] => 17/200291 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 87 [patent_no_of_words] => 9326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200291
Multi-gate devices with multi-layer inner spacers and fabrication methods thereof Mar 11, 2021 Issued
Array ( [id] => 17262873 [patent_doc_number] => 20210375858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Gate Isolation for Multigate Device [patent_app_type] => utility [patent_app_number] => 17/199777 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199777
Gate isolation for multigate device Mar 11, 2021 Issued
Array ( [id] => 17871034 [patent_doc_number] => 20220293771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => LDMOS With An Improved Breakdown Performance [patent_app_type] => utility [patent_app_number] => 17/199153 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199153
LDMOS with an improved breakdown performance Mar 10, 2021 Issued
Array ( [id] => 18304565 [patent_doc_number] => 11626482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Air spacer formation with a spin-on dielectric material [patent_app_type] => utility [patent_app_number] => 17/192134 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 9379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192134 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192134
Air spacer formation with a spin-on dielectric material Mar 3, 2021 Issued
Array ( [id] => 18263096 [patent_doc_number] => 11610805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Replacement material for backside gate cut feature [patent_app_type] => utility [patent_app_number] => 17/186839 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186839 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186839
Replacement material for backside gate cut feature Feb 25, 2021 Issued
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