Search

Vu B Hang

Examiner (ID: 4126, Phone: (571)272-0582 , Office: P/2672 )

Most Active Art Unit
2672
Art Unit(s)
2625, 2671, 2654, 2672
Total Applications
753
Issued Applications
515
Pending Applications
46
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17359946 [patent_doc_number] => 20220020742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/180989 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180989
Semiconductor devices having asymmetrical structures Feb 21, 2021 Issued
Array ( [id] => 17925985 [patent_doc_number] => 11469249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Method of fabricating electronic devices comprising removing sacrificial structures to form a cavity [patent_app_type] => utility [patent_app_number] => 17/172956 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 12112 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172956
Method of fabricating electronic devices comprising removing sacrificial structures to form a cavity Feb 9, 2021 Issued
Array ( [id] => 17509393 [patent_doc_number] => 20220102496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => DEVICE WITH EPITAXIAL SOURCE/DRAIN REGION [patent_app_type] => utility [patent_app_number] => 17/168002 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168002
Device with epitaxial source/drain region Feb 3, 2021 Issued
Array ( [id] => 17536925 [patent_doc_number] => 20220115534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => LATERALLY DIFFUSED MOSFET AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/165165 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165165
Laterally diffused MOSFET and method of fabricating the same Feb 1, 2021 Issued
Array ( [id] => 18645743 [patent_doc_number] => 11769824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Gallium nitride transistor with a doped region [patent_app_type] => utility [patent_app_number] => 17/165697 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4582 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165697
Gallium nitride transistor with a doped region Feb 1, 2021 Issued
Array ( [id] => 16858594 [patent_doc_number] => 20210159339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION [patent_app_type] => utility [patent_app_number] => 17/161534 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161534 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161534
Semiconductor device having doped epitaxial region and its methods of fabrication Jan 27, 2021 Issued
Array ( [id] => 17956479 [patent_doc_number] => 11482594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Semiconductor devices with backside power rail and method thereof [patent_app_type] => utility [patent_app_number] => 17/159309 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 11984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159309
Semiconductor devices with backside power rail and method thereof Jan 26, 2021 Issued
Array ( [id] => 17978818 [patent_doc_number] => 11495693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Semiconductor memory device and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/159168 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3788 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159168
Semiconductor memory device and fabrication method thereof Jan 26, 2021 Issued
Array ( [id] => 17010865 [patent_doc_number] => 20210242026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, RECORDING MEDIUM, AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/159252 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159252
Method of manufacturing semiconductor device, recording medium, and substrate processing apparatus Jan 26, 2021 Issued
Array ( [id] => 18249110 [patent_doc_number] => 11605710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Transistor with air gap under source/drain region in bulk semiconductor substrate [patent_app_type] => utility [patent_app_number] => 17/155469 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6975 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155469
Transistor with air gap under source/drain region in bulk semiconductor substrate Jan 21, 2021 Issued
Array ( [id] => 17862998 [patent_doc_number] => 11444160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Integrated circuit (IC) structure with body contact to well with multiple diode junctions [patent_app_type] => utility [patent_app_number] => 17/155182 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7280 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155182
Integrated circuit (IC) structure with body contact to well with multiple diode junctions Jan 21, 2021 Issued
Array ( [id] => 17302966 [patent_doc_number] => 20210398805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => Epitaxial Growth Process for Semiconductor Device and Semiconductor Device Comprising Epitaxial Layer Formed By Adopting the Same [patent_app_type] => utility [patent_app_number] => 17/141341 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141341 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141341
Epitaxial growth process for semiconductor device and semiconductor device comprising epitaxial layer formed by adopting the same Jan 4, 2021 Issued
Array ( [id] => 17709004 [patent_doc_number] => 20220209012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => TWO-ROTATION GATE-EDGE DIODE LEAKAGE REDUCTION FOR MOS TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/135541 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135541
TWO-ROTATION GATE-EDGE DIODE LEAKAGE REDUCTION FOR MOS TRANSISTORS Dec 27, 2020 Pending
Array ( [id] => 16850704 [patent_doc_number] => 20210151449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => STACKED VERTICAL TRANSISTOR ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND PROGRAMMABLE INVERTER DEVICES [patent_app_type] => utility [patent_app_number] => 17/133387 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133387
Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices Dec 22, 2020 Issued
Array ( [id] => 17692504 [patent_doc_number] => 20220199797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => LOCALIZED SPACER FOR NANOWIRE TRANSISTORS AND METHODS OF FABRICATION [patent_app_type] => utility [patent_app_number] => 17/131467 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131467 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131467
LOCALIZED SPACER FOR NANOWIRE TRANSISTORS AND METHODS OF FABRICATION Dec 21, 2020 Pending
Array ( [id] => 17803418 [patent_doc_number] => 11417731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Semiconductor device including a field effect transistor and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/128153 [patent_app_country] => US [patent_app_date] => 2020-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 63 [patent_no_of_words] => 14078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128153
Semiconductor device including a field effect transistor and method of fabricating the same Dec 19, 2020 Issued
Array ( [id] => 16936591 [patent_doc_number] => 20210202480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => COINTEGRATED SEMICONDUCTOR STRUCTURES FOR DIFFERENT VOLTAGE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/127424 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127424
Method of cointegrating semiconductor structures for different voltage transistors Dec 17, 2020 Issued
Array ( [id] => 16731116 [patent_doc_number] => 20210098264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => Selective Removal of an Etching Stop Layer for Improving Overlay Shift Tolerance [patent_app_type] => utility [patent_app_number] => 17/121338 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121338
Semiconductor device having improved overlay shift tolerance Dec 13, 2020 Issued
Array ( [id] => 16731159 [patent_doc_number] => 20210098307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/120689 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120689
Semiconductor device structure with tapered contact and method for forming the same Dec 13, 2020 Issued
Array ( [id] => 17676787 [patent_doc_number] => 20220189954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => SEMICONDUCTOR DEVICE WITH DIFFUSION SUPPRESSION AND LDD IMPLANTS AND AN EMBEDDED NON-LDD SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/117421 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117421 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117421
Semiconductor device with diffusion suppression and LDD implants and an embedded non-LDD semiconductor device Dec 9, 2020 Issued
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