Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same | Patent Publication Number 20200194446

US 20200194446 A1
Patent NumberUS 10797061 B2
Application Number16221942
Filled DateDec 17, 2018
Priority DateDec 17, 2018
Publication DateJun 18, 2020
Original AssigneeWestern Digital
Inventor/ApplicantsRahul Sharangpani
Adarsh RAJASHEKHAR
Akio Nishida
Srikanth Ranganathan
Toshikazu IIZUKA
Fei ZHOU
Srikanth RANGANATHAN
Toshihiro Iizuka
Akio NISHIDA
Raghuveer S. MAKALA
Adarsh Rajashekhar
Rahul SHARANGPANI
Raghuveer S. Makala
Fei Zhou
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