INTEGRATED CIRCUIT LAYOUT AND METHOD THEREOF | Patent Publication Number 20220093587

US 20220093587 A1
Patent Number-
Application Number17025917
Filled DateSep 18, 2020
Priority DateSep 18, 2020
Publication DateMar 24, 2022
Original AssigneeTaiwan Semiconductor Manufacturing Company
Current AssigneeTaiwan Semiconductor Manufacturing Company
Inventor/ApplicantsChien-Yuan CHEN
Hau-Tai SHIEH
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