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1. R. FarjadR. Farjad3103,, A 16-port FCC-Compliant 10GBASE-T Tx+Hybrid with 76dBc SFDR. Feb 2012; |
2. R. FarjadR. Farjad3103,, Low-Power High Density 10GBASE-T Ethernet Transceiver. Aug 2011; |
3. R. FarjadR. Farjad3103,, A 33-mW 8-Gb/s CMOS Clock Multiplier and CDR for Highly Integrated I/O. Sept 2004; |
4. R. FarjadR. Farjad3103,, A 2nd -0rder Semi-Digital Clock Recovery Circuit Based on Injection locking. Dec 2003; |
5. R. FarjadR. Farjad3103,, 0.622-8.0Gbps 33mW data recovery and clock generation circuit with high noise tolerance for high density integration. Oct 2003; |
6. R. FarjadR. Farjad3103,, "0.622-8.0Gbps 150mW Serial IO Macrocell with Fully Flexible Preemphasis and Equalization. Jun 2003; |
7. R. FarjadR. Farjad3103,, A Discrete Loop Analysis for Jitter Peaking in Delay-Locked Loops and Phase-Locked Loops. Apr 2003; |
8. R. FarjadR. Farjad3103,, A 2nd-Order Semi-Digital Clock Recovery Circuit Based on Inaction locking. Feb 2003; |
9. R. FarjadR. Farjad3103,, A Low-Power Multi-GHz Multiplying DLL for Low-jitter Clock Synthesis in Data Communication VLSI Chips. Dec 2002; |
10. R. FarjadR. Farjad3103,, A 0.2-2GHz 12-mW Multiplying DLL for Low-jitter Clock Synthesis in Highly Integrated Data Communication Chips. Feb 2002; |
11. R. FarjadR. Farjad3103,, A 0.3-um CMOS 8-Gb/s 4-PAM Serial Link Transceiver with Channel Equalization. May 2000; |
12. R. FarjadR. Farjad3103,, A 0.3-um CMOS 8-Gb/s 4-PAM Serial Link Transceiver. Jun 1999; |
13. R. FarjadR. Farjad3103,, A 0.4um CMOS 10-Gbps 4-PAM Serial Link Transmitter with Output Pre-emphasis. May 1999; |
14. R. FarjadR. Farjad3103,, A 0.5um CMOS 4Gbps transceiver with data recovery using oversampling. May 1998; |
15. R. FarjadR. Farjad3103,, A Equalization Scheme for 10Gb/s 4PAM Signaling over Long Cables. Aug 1997; |
16. R. FarjadR. Farjad3103,, A 0.6um CMOS 4Gb/s Transceiver with Data Recovery using Oversampling. Jun 1997; |