Search
Patexia Prashant Agrawal’s

Prashant Agrawal > Papers

Paper Listing

Conference:
1.
P. Agrawal, Early Exploration for Platform Architecture Instantiation with Multi-mode Application Partitioning. "Design Automation Conference (DAC)": June 2013;
2.
P. Agrawal, Data Memory optimization in LTE Downlink. "International Conference on Acoustics, Speech, and Signal Processing (ICASSP)": 2013;
3.
P. Agrawal, Partitioning and assignment exploration for multiple modes of IEEE 802.11n modem on heterogeneous MPSoC platform. "Euromicro Conference on Digital System Design (DSD)": 2012;
4.
P. Agrawal, High level analysis of trade-offs across different partitioning schemes for wireless applications. "IEEE Workshop on Signal Processing Systems (SIPS)": 2011;
5.
P. Agrawal, Performance optimizations for distributed real-time text indexing. "High Performance Computing Conference": 2009;
6.
P. Agrawal, Optimization of BLAS on the Cell Processor. "High Performance Computing Conference": 2008;
7.
P. Agrawal, Methodology for Thermal Aware Topologies and Partitioning with Better Lateral Spreading. "International Conference on Microelectronics": 2008;
8.
P. Agrawal, A path based modeling approach for dynamic power estimation. "ACM Great Lakes Symposium on VLSI (GLSVLSI)": 2007;
9.
P. Agrawal, A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs. "IEEE Computer Society Annual Symposium on VLSI": 2007;
10.
P. Agrawal, An Approach for Pre-Silicon Power Modeling. "International Conference on Computing: Theory and Applications (ICCTA)": 2007;
Menu