Igor Lusetsky > Biography
Biography Information
02/2014 Independent Semiconductor Memory Developer
SRAM cell design, architecture and characterisation. SRAM and product yield ramp up
Design, architecture and concept definition of embedded flash memory. eFlash characterisation, yield ramp and reliability improvement
7/2011-01/2014 Member of Technical Staff, GLOBALFOUNDRIES, Singapore
o Designed and defined a concept of flash memory cell (NVM). Provided expert guidance resulted in enhanced product performance and reliability, performing product characterization and statistical data analysis. Analyzing design and performance trade-offs of existing NVM product provided guidance for improving product yield and reliability
o SRAM Design engineer developed high-density SRAM devices and integrated them into the 28nm CMOS process flows, optimized SRAM cells for product performance and reliability, yield and manufacturability. Proposed and implemented device and process solutions to ramp up the SRAM and product yield
06/2009-07/2011 Senior Technical Manager, SMIC
o Leading development engineer responsible for design and development of SRAM bit cell based on 40nm CMOS process technology, performing electrical characterisation and statistical data analysis, generating methodologies for continuous process/device/yield improvements
SRAM cell design, architecture and characterisation. SRAM and product yield ramp up
Design, architecture and concept definition of embedded flash memory. eFlash characterisation, yield ramp and reliability improvement
7/2011-01/2014 Member of Technical Staff, GLOBALFOUNDRIES, Singapore
o Designed and defined a concept of flash memory cell (NVM). Provided expert guidance resulted in enhanced product performance and reliability, performing product characterization and statistical data analysis. Analyzing design and performance trade-offs of existing NVM product provided guidance for improving product yield and reliability
o SRAM Design engineer developed high-density SRAM devices and integrated them into the 28nm CMOS process flows, optimized SRAM cells for product performance and reliability, yield and manufacturability. Proposed and implemented device and process solutions to ramp up the SRAM and product yield
06/2009-07/2011 Senior Technical Manager, SMIC
o Leading development engineer responsible for design and development of SRAM bit cell based on 40nm CMOS process technology, performing electrical characterisation and statistical data analysis, generating methodologies for continuous process/device/yield improvements