Special Instruction Set Architecture

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Prize $5,000

Status Competed

Description

Patexia seeks prior art for US Patent 5,991,545 (US ‘545) which allegedly describes a special instruction set architecture of a central processing unit (CPU) which tackles various problems accompanying the adoption of a fixed length instruction format having a smaller bit number (16 bits) than that of a data word length (32 bits).

Various instructions of an instruction set can be executed by the CPU, and

the instructions have a fixed instruction length of a first bit length (16 bits)
the instructions set includes conditional/unconditional branch instructions
each of the branch instructions has an area comprising a displacement value
the displacement area of the conditional branch instruction(s) has a different bit width from that of the unconditional branch instruction(s)

The CPU includes,

an instruction memory
- stores instructions of an instruction set
an instruction register
- coupled to the instruction memory
- fetches a one instruction that has a displacement/offset value
decode means
- decode the fetched one instruction in the instruction register
a program counter (PC)
- stores an address of the fetched one instruction
an execution unit
- performs an operation of data, whose maximum word length is a second bit length (such as 32 bits)
- performs an operation for immediate data having a bit length of greater than first bit length (16 bits)
- receives data located at an address concatenated from the address stored at the PC with the displacement value

Further explanation on the present embodiment based on a specific setting

In processing a data word of 32 bits in length, multiple immediate values are utilized by the CPU, some of them may be smaller than the length of the 16 bit instruction, while others might be larger than 16 bits. Here is this embodiment, the length of an instruction is 16 bits.

Problem: The instruction has a fixed length of 16 bits, the length of data word is 32 bits, thus it’s not realistic and practical to expect all immediate values to be fitted in the length of an instruction since some of them will be larger than 16 bits.

Solution: Use the value of a register (such as the program counter, PC) plus the relative address (offset/displacement), so as to select immediate value of more than 16 bits length. For more detailed explanation, please find column 21, line 25 - 52 and figure 13 of US Patent 5,991,545 (US ‘545).

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Details

Prior Art Search

This is a Prior Art Search contest aimed at determining if a patent idea was known and publicly available before a patent was filed.

This contest will close on Sunday, September 14th, 2014 at 11:59 PM PST.

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Special Instruction Set Architecture

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