CONTEST
Competed
$4,500
This contest is closed.
Problem
Patexia is looking for descriptions of fabricating two semiconductor layers and mounting them on top of each other to make a 3D integrated circuit.
Submitted documents describing this system must be:
- filed or published before 09/22/1995
- not on the known references list
The entire submission must describe a fabrication method with the following steps:
- creating what will be the base layer by making a semiconductor layer a substrate, and a layer of multiple independent devices arranged on top
- creating what will be the chips that are mounted on the base layer by making a semiconductor layer with the same composition as the base layer
- taking the layer that will become the chips and layering an auxiliary substrate on top, while reducing the thickness of the bottom substrate
- cutting the layer with the thin substrate and auxiliary substrate into individual chips and testing to see if the devices are defective
- aligning and mounting the chips onto the base layer, leaving space between chips
- removing the auxiliary substrate, smoothing out the space between chips (or planarizing), and electrically connecting the devices in the chips with the devices in the base layer
Figure. Diagram showing the process of how the chips are mounted onto the base layer
This contest is for a prior art search for US Patent 5,563,084, with a focus on claim 1.
Questions
| # | Question | Value |
|---|---|---|
| 1 | Is the reference either a US patent filed, a foreign patent published, or a non-patent document published before September 22nd, 1995? | T/F |
| 2 | Does the reference show that chips are aligned and mounted side-by-side on the top surface of a base layer, while maintaining some space between chips? | 40 |
| 3 | (3a) Does the reference further show that the chips and the base layer are both made from semiconductor layers with (a) a substrate, and (b) circuits and devices layered on top? | 20 |
| 4 | Does the reference show that the semiconductor layer that will become the chips additionally has (c) an auxiliary substrate layered on top, while the (a) substrate on the bottom has its thickness reduced? | 20 |
| 5 | (5a) Does the reference further show that the chip are made by (1) cutting the semiconductor layer with the thinner substrate and auxiliary substrate into individual chips and (2) testing to see if the circuits and devices in each chip are defective? | 10 |
| 6 | After the chips are mounted, does the reference show that the auxiliary substrate is removed, the space between the chips are smoothed out (or “planarized”), and the chips are electrically connected to the circuits and devices in the base layer? | 10 |
Additional Notes
This is a Prior Art Search contest aimed at determining if a patent idea was known and publicly available before a patent was filed.
+5 bonus points will be awarded for non-patent literature and for foreign language references.
This contest will close on Sunday, July 12th, 2015 at 11:59 PM PST.
Please review the Contest Rules. For more information on how to submit to this Contest type, please read the Intro to Prior Art Search page.
