Patexia seeks valid US patents that include claims describing a very long instruction word (VLIW) processor architecture that is also described in combination and implemented alongside multithreading and nested hardware loops.

In the pursuit of faster processors, instruction level parallel processing (ILP) was researched as a method to significantly speed up processing speeds by allowing multiple operations to occur simultaneously. By allowing for operations to happen simultaneous, parallel processing could be paired with continuing advances in processor speed to bring about significant advances in computer architecture.

However, traditional approaches to ILP heavily depended on the hardware for implementation. For example, when multiple operations are queued up for simultaneous execution, the processor hardware needed to check for any dependencies. If an operation (i) requires the results of another operation (k), it is impossible for both operations (i and k) to occur at the same time. With the added hardware complexity, power consumption would increase accordingly.

VLIW was developed in response to these hardware concerns by determining the relationship and scheduling of dependent operations (i and k) when the program is compiled by the software compiler. These operations are put into a very long instruction word which the processor hardware can break apart into parallel operations without any further analysis, which is also how the processor architecture gets its name.

Additional techniques were developed independent of VLIW to help increase the efficiency of ILP, specifically: multithreading and hardware loops (also known as loop unrolling or hardware loop prediction).

Multithreading is the processor hardware’s ability to process multiple threads (essentially multiple tasks) in parallel. This is different from multiprocessor techniques (such as multi-core systems). Multithreading requires (and also benefits from) threads sharing the same resources from the same core, while multiprocessing has operations occurring on separate cores with separate resources.

Multithreading is uncommon to VLIW processor architectures largely due to the fact that multithreading is also software intensive and that VLIW tends to work better with multiple cores handling intensive operations separately.

Hardware loops is the ability to predict the operations that will occur in each iteration of a loop, optimize the operations that can occur in parallel, and buffer them for the hardware to execute when available.

For example, if the program implements a for loop for a set of arithmetic operations, the method will:

• pre-calculate a loop for a set number of iterations
• rewrite the entire set of operations as a series of operations without the loop structure
• analyze for operations that can occur in parallel
• store these operations so that the processor can execute them when available

Hardware loops is a technique that predates VLIW. While not developed specifically for it, hardware loops can greatly benefit the efficiency of VLIW architectures when they encounter loops.

While prevalent individually, these technologies are an unusual combination. It is this noteworthy intersection of all three methods that Patexia seeks valid US patents and claims for.

Questions

1. Does the US patent have an earliest effective filing date from between January 1st, 1995 to December 31st, 2004?
2. Is the US patent currently not expired or abandoned ?
3. Does the claims of the US patent describe a circuit architecture for a digital signal processor?
4. In the same independent claim or in a subsequent dependent claim, does the US patent describe the digital signal processor implementing a very long instruction word (or VLIW) processor architecture?
5. In the same independent claim or in a subsequent dependent claim, does the US patent describe the VLIW processor architecture implemented alongside multithreading or is question 6 answered as “Yes”?
6. In the same independent claim or in a subsequent dependent claim, does the US patent describe the VLIW processor architecture implemented alongside hardware loops or is question 5 answered as “Yes”?

Submission Guidelines

For each US patent, either question 5 or question 6 must be answered “Yes” to receive full credit. Therefore:

• A US patent that answers “Yes” to 1, 2, 3, 4, and 5, but “No” to 6 will receive a full score.
• A US patent that answers “Yes” to 1, 2, 3, 4, and 6, but “No” to 5 will receive a full score.