CONTEST
Competed
$5,000
This contest is closed.
Sub poena
technologyManil Dev
technologyScott Locke
technologyGone SRK
technologyGracie Allen
technologySamuel Flynn
technologyMohita Agarwal
technologyCharu S
technologymadhu
technologyBimla Kumari
technologyAmit Aswal
technologyRashmi Pandey
technologyYogesh Bansal
technologySimon Sunatori
technologyProblem
Patexia seeks prior art for US Patents 5,812,789 (‘789) and 6,058,459 (‘459), with a focus on claims 1, 15, and 29 of US ‘789 and claims 1, 11, and 16 of US ‘459. The patent allegedly describes a method to allow two components to access a common shared memory unit in a manner that organizes access by priority and provides for sufficient bandwidth to allow access without negatively impacting performance by any component.
The system described in the patent includes a first device, and an audio and/or video decompression and/or compression device (or “decoder”) capable of operating in real time. Both components require access to a shared memory unit via a memory interface for their operation. This memory interface includes an arbiter to negotiate between the two components when one of them is requesting access to the memory.
The arbiter manages this priority by implementing a state machine algorithm. Each component, the first device and the decoder, has a priority. When a request is made by the decoder to access the memory, the result of the request is dependent on the state of the arbiter. If the arbiter is in its:
- idle state, the decoder is provided access
- busy state, the decoder’s request is queued
- queue state, the decoder’s request is queued based on its priority and the priority of any other queued requests
Figure 1. Block Diagram of the Shared Memory Access System
Questions
| # | Question | Value |
|---|---|---|
| 1 | Was the reference filed or published before August 26th, 1996? | T/F |
| 2 | Does the reference describe a system that includes a memory unit, a first bus, a first device requiring memory access, and a decoder requiring memory access for real time operation? | 10 |
| 3 | Does the memory unit include a memory interface for the first device and the decoder to access the memory via the first bus, and only through this bus, with sufficient bandwidth to allow simultaneous access by both devices without negatively impacting real time performance by the decoder? | 30 |
| 4 | Does the system include an arbiter with an idle, busy, and queue state that is linked to the first device and decoder in order to selectively allow each access to the memory? | 20 |
| 5 | Do the first device and decoder each have a device priority and are they each capable of generating a request to access the memory? | 10 |
| 6 | Is the decoder request granted if the arbiter is in its idle state, queued if the arbiter is in its busy state, or queued by its priority and the priority of any other queued requests if the arbiter is in its queue state? | 30 |
Additional Notes
This is a Prior Art Search contest aimed at determining if a patent idea was known and publicly available before a patent was filed.
This contest will close on Sunday, March 2nd, 2014 at 11:59 PM PST.
Please review the Submission Rules and Style Guidelines as well as the Style Guidelines specific to this type of contest.
