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Patexia Contest

CONTEST

Competed
Prize
$10,000
DEADLINE
This contest is closed.
Winner

Krste Asanovic

technology
Runner Up
Runner Up

Gracie Allen

technology
Runner Up

Rucapillan IP

technology
Runner Up

Krish Dev

technology
Runner Up

Amit Aswal

technology
Runner Up

Paton Paton

technology
Runner Up

David Heckadon

technology
Runner Up

Satyam Singh

technology
Runner Up

Milind Singhal

technology
Runner Up

Yogesh Bansal

technology

Problem

Patexia contests ask you to find, submit, and explain references that respond to our research criteria. If you are new, see patent and prior art basics and tips for Patexia's prior art contests, and refer to the submission notes below. The following questions will help you understand specifically what we are looking for in this study.

In this contest we are seeking prior art; published examples of an idea or invention before a specific date.

Problem Definition
Patexia seeks prior art for US Patent 5,924,119 (‘119) - “Consistent packet switched memory bus for shared memory multiprocessors.” The patent allegedly describes a system for sharing a memory microprocessor between multiple processors using a packet switched bus which transfers data between processors, I/O devices, cache memories and main memories. The bus protocol allows multiple copies of data to be updated under the control of different processors while still ensuring that all processors and all I/O devices have access to consistent values for all data at all times.

The basic system architecture has been illustrated below in Figure 1 and operates as follows:

  • The main memory 13 is connected to the packet switched bus 26.
  • Multiple processors 12 (12aa, 12aj, …) are connected to  multiple cache memories 16 (16aa, 16ba, …) and from there are connected to packet switched buses 15 (15a, 15b, …).
  • Packet switched buses 15 (15a, 15b, …) transfer data between the main memory and the processors using the main packet switched bus 26.
  • The data are queued and transferred in such an order to ensure consistency of values between processors and I/O devices even when multiple copies of data are being updated.

Figure 1. A shared memory multiprocessor system


Questions
When entering a contest, Patexia’s system will ask you the following questions. Contestants should attempt to locate sources that answer these questions and submit a concise explanation as to why the source(s) answers our question(s). This explanation should specifically indicate where in the reference we can find the required supporting information. If you do not provide adequate explanations on how to locate the desired information in your reference, your entry will not be considered for a prize or in the final contest rankings.

Entries must answer all contest questions. All sources must be clearly dated or they will not be considered.

  1. Was the source published before November 30th, 1990?
  2. Does the source describe a shared memory multiprocessor system with a main memory, multiple processors, I/O Devices, and cache memories?
  3. Are the cache memories coupled to the processor (see Figure 1)?
  4. Is there a packet switched bus coupled to the main memory and the cache memories for transferring commands, memory addresses, and data?
  5. Is data transfer in compliance with a predefined set of memory transactions?
  6. Does the system allow memory transactions that cause multiple copies of data to be updated at different times under the control of different processors?
  7. Is each memory transaction composed of a request packet followed at a later time by a reply packet, thereby enabling the request and reply packets for multiple transactions to be time interleaved on the bus?
  8. Are all memory transactions selected in such a way to enforce a consistency protocol that ensures all processors and all I/O devices have access to consistent values for all data stored in the cache memories, including data represented by multiple copies?
  9. [User Survey Question] Can you provide us with more information regarding your qualifications to enter this contest? (no reference needed, please provide a short list of your relevant background or qualifications.)
  10. [User Survey Question] Can you provide us with more information regarding the time you spent researching the contests? (no reference needed, please provide an estimate of the time you spent researching this contest.)
  11. [User Survey Question] Can you provide us with more information regarding the resources and databases you searched for this contest? (no reference needed, please provide a short list of sources that you used to research this contest.)
Have a question about this contest? Ask a Question

Questions

#QuestionValue
1Was the source published before November 30th, 1990? 0
2Does the source describe a shared memory multiprocessor system with a main memory, multiple processors, I/O Devices, and cache memories? 0
3Are the cache memories coupled to the processors (see Figure 1)? 0
4Is there a packet switched bus coupled to the main memory and the cache memories for transferring commands, memory addresses, and data? 0
5Is data transfer in compliance with a predefined set of memory transactions? 0
6Does the system allow memory transactions that cause multiple copies of data to be updated at different times under the control of different processors? 0
7Is each memory transaction composed of a request packet followed at a later time by a reply packet, thereby enabling the request and reply packets for multiple transactions to be time interleaved on the bus? 0
8Are all memory transactions selected in such a way to enforce a consistency protocol that ensures all processors and all I/O devices have access to consistent values for all data stored in the cache memories, including data represented by multiple copies? 0
9[User Survey Question] Can you provide us with more information regarding your qualifications to enter this contest? (no reference needed, please provide a short list of your relevant background or qualifications.) 0
10[User Survey Question] Can you provide us with more information regarding the time you spent researching the contests? (no reference needed, please provide an estimate of the time you spent researching this contest.) 0
11[User Survey Question] Can you provide us with more information regarding the resources and databases you searched for this contest? (no reference needed, please provide a short list of sources that you used to research this contest.) 0

Additional Notes

Submission Notes

  • The submission deadline is 11:59 PM PST on September 23rd, 2013.
  • Entries must be in English.
  • All questions should be answered (yes or no) based on your reference(s).
  • All answers should include a clear explanation of how each reference directly answers the questions.
  • If you do not provide adequate explanations for your answers, your entry will not be considered for a prize or in the final contest rankings.
  • When submitting foreign references, please provide a translation of key sections in the explanation box.
  • Please use “Ask a Question” to post general questions or feedback about the contest to the community.
  • For specific questions, you can contact us directly by email at contests@patexia.com.
  • All submissions are subject to Patexia's contest legal terms. Failure to follow these rules may lead to disqualification from the contest.

Selection Criteria and Prize Distribution
Patexia will evaluate each response to ensure that each question has been satisfactorily answered. We will determine the contest winner and runners-up based first on the number of verified "yes" responses and second on the order in which the responses were submitted. Each submission will be awarded an average weighted relevancy score. In the event of a tie score for the same reference we will favor the earlier entry. We will award 80% of the contest prize to the winning submission, and we will distribute the remaining 20% among the qualifying runners-up. Up to 10 runners-up will be rewarded, with each runner-up receiving a minimum of $200. If the owner of the winning entry was referred to Patexia by another user, a $800 referral prize will be subtracted from the winner's 80% award and given to whomever was responsible for the referral. Winner selection is based entirely on community responses to Patexia's research questions and does not constitute a legal opinion on patent validity or related litigation.

Known References
US4426681
US4442487
US4451880
US4535448
US4622631
US4843542

Andrew W. Wilson, Jr., "Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors," Computer Architecture Conference (IEEE/ACM), 1987, pp. 244-252.

David V. James edited by Dubois et al., "Cache and Interconnect Architectures in Multiprocessors, SCI (Scalable Coherent Interface) Cache Coherence, " Academic Publishers, 1990, pp. 189-208.

 

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