Patexia seeks prior art for US Patent 6,744,692 (US ‘692), which allegedly describes a method of improving the efficiency of a memory access operation by allowing data transfer operations to be conducted in parallel between a rewritable nonvolatile memory and an external host through a controller and buffer memory.

The method is accomplished by a memory system connected to an external host  with the following components:

• a rewritable nonvolatile flash memory (or “memory”)
• a buffer memory (or “buffer”)
• and a memory controller

This memory controller conducts three data transfer operations:

1. a first data transfer with the external host
2. a second data transfer with the memory
3. and a third data transfer with the buffer

This system is able to save time by allowing two operations to be conducted in parallel during a time cycle (which may be one or more clock cycles):

1. allowing the third data transfer between controller/buffer to occur in parallel with the first data transfer between controller/host
2. and allowing the third data transfer between controller/buffer to occur in parallel with the second data transfer between controller/memory

By doing so, a potential embodiment can save time by allowing write operation requests by the host to occur in the following manner:

• during a first time cycle, having write data transferred from the external host to the controller
  while during the same cycle, having write data from a previous host/controller transfer, now being transferred from the buffer to the controller

• during a second time cycle, having write data transferred from the controller to the now vacant buffer
  while during the same cycle, having write data from the previous buffer/controller transfer, now being transferred from the controller to the memory

Because the buffer is able to transfer data to the controller at a rate much faster than the host can transfer to the controller, the host is never tied up and transfers are kept to a minimum number of clock cycles.

However, while this is a potential embodiment, prior art may cover any combination of the operations occurring in parallel so long as the third and first data transfers, or the third and second data transfers occur in parallel.

Figure 1. Block Diagram of the Components of the Flash Memory Buffer Apparatus

Figure 2. Overview of the Parallel Operation Process

Questions

1. Was the reference filed or published before February 7th, 2002? (True/False)
2. Does the reference describe an external host that connects to a memory system with a rewritable nonvolatile flash memory, a buffer memory, and a controller? (15 points)
3. Does the reference describe three data transfer processes: a first (1st) between the external host and the controller, a second (2nd) between the memory and the controller, and a third (3rd) between the buffer and the controller? (20 points)
4. Does the controller control the third (3rd) data transfer to and from the buffer and the controller in a time sharing manner (e.g. during one time cycle a transfer to the buffer occurs, while during the next time cycle a transfer from the buffer occurs)? (25 points)
5. Does the controller enable the first (1st) or second (2nd) data transfers to occur in parallel with the third (3rd) data transfer (e.g. during a time cycle when a transfer to the buffer is occurring, a parallel transfer to memory is also occurring at the same time; or another similar pair of transfers occurring in parallel)? (30 points)
6. Does the reference describe the third (3rd) data transfer between controller and buffer occurring at twice the rate as the first (1st) data transfer between controller and external host? (10 points)