Patexia seeks prior art for US Patent 6,233,174 (US ‘174) that allegedly describes a partial erasure method which reads selected cells from two different allocation groups on a nonvolatile memory into a data latch, overwrites the latched data from one of the allocations with erase data, proceeds with erasing the selected cells on the nonvolatile memory, and finally writes the latched data for both allocations back onto the nonvolatile memory.

Figure 1. Block Diagram of the Components of the Nonvolatile Memory System

Questions

1. Was the reference filed or published before February 16th, 1998? (True/False)
2. Does the reference describe a nonvolatile memory system which includes a controller, a data latch, and a plurality of memory cells allocated to one of two groups?
3. Does the controller provide a partial erase operation which selects memory cells from each group, stores the data from the selected cells to the data latch, and writes erase data from an outside source onto the latched data from the second group?
4. Does the controller continue the partial erase operation by erasing the data left on the selected memory cells from both groups, and afterwards programs the data pertaining to both groups from the data latch onto the respective memory cells?