Update (July 10, 2012): From the sponsoring semiconductor company -- "Our Chief Architect would like to invite the participants who submit the top three answers to a private dinner (transportation and accommodation not included). Plus, we are hoping to pick our next recruit from the participants of this contest."

What options exist to optimize (on architectural level; most likely based on coefficient profile characteristic) the power consumption of the following Finite Impulse Response Filter (FIR) without leaving time-domain filtering?

EXISTING ARCHITECTURE  

• Length of required FIR instances: N*100 Taps (N= 1 to10)
• Data Rate: 1 Gsample/s
• Input Data Wordlength: 10b
• Coefficient wordlength: 14b (low update rate)
• Process Technology: 40nm CMOS (or older)
• Carry-Save-based Modified Bitplane Filters with Booth-encoded Coefficients. See [Noll93] for details.
• Polyphase structure with n=2 parallel FIRs (1 full-rate full-length FIR replaced by 3 half-rate half-length sub-FIRs). All higher order polyphase structures turned out to be less optimum in power consumption. See literature (e.g. [Parhi97]) for details.
• Each FIR macro of N*100 taps combines 3 sub-FIRs namely Odd/Even/Sum (Ho/He/Ho+He) of half length (N/2*100) running half rate (500MHz)
• FIR macros are implemented as chain of cascaded 50-Tap units. 

              - Cascaded segments support segment-wise power down from upper to lower taps (left to right In page 4 figure). Structure does not support individual power down of  intermediate segments.

              - Final adder just required for combining output data of 4 bitplanes (Each bitplane delivers full-length FIR output)

              - FIR core is using mirror adder cell with minimum sized devices and dynamic latches achieving the optimum degree of pipelining of 2 full-additions per cycle.

• Each sub-FIR combines 4 Booth-Bitplanes processing the coefficients in chunks of 4b (see [Noll93] for details)

Sample Sub-FIR Architecture

• Bitplanes #0,#1,#2 process 4bit coefficients & Bitplane #3 processes 2bit (Odd/Even) or 3bit (Sum)
• 14b Coefficients co<13:0> & 10b Data x<9:0> for Odd/Even Sub-FIR
• 15b Coefficients co<14:0> & 11b Data x<10:0> for Sum Sub-FIR

A 500-Tap Booth-Bitplane

10 cascaded 50-Tap Sub-Bitplanes X= Data, CO= Coefficient, CCE= Coefficient Capture Enable

50-Tap Sub-Bitplane

Processing 2 Booth-Coefficient Digits per Tap

Combining bit plans

Final Adder: Combining output data of 4 Bitplanes (output remains carry-save number representation)

LIMITATIONS

1) Saving in Power should not increase Area by more than 20%.

• Custom implementation of FIR cores using minimum-sized devices and dynamic storage elements guarantees minimum power dissipated by functional switching (clock excluded).
• Coefficient update rate is low (< 1 update per 1000 cycles per tap), Typical coefficient profiles mostly show near-zero taps, but significant coefficient values may occur at any location. E.g.,

2) Dynamic power breakdown for typical coefficient profiles leads to 50% clock, 50% functional switching.

• Note: This does not indicate poor design of clock network. Instead it is the result of power-aware design of FIR core in combination with characteristic coefficient profiles where significant sections are not activated.

3) On circuit level we are confident to have optimized all relevant aspects (minimum-sized devices, mostly using HVT devices, lowering supply as much as possible, using dynamic storage elements)

REFERENCES

[Noll93] VLSI Implementation for Image Communication. In: Pirsch P. editor, Advances in Image Communication 2. Amsterdam: Elsevier; 1993; p. 171 - 213.

[Parhi97] Parker DA, Parhi KK. Low-Area/Power Parallel FIR Digital Filter Implementations. Journal of VLSI Signal Processing. 1997; 17: 75–92.

SUBMISSION NOTES

• Submission deadline August 5, 2012
• All work must be original and prepared by a single author
• Maximum of one entry per person allowed
• Entries must be in English
• All submissions are subject to Patexia's contest legal terms
• Failure to follow these rules may lead to disqualification from the contest
• For questions, email contests@patexia.com

Existing Architecture

• All work must be original and prepared by a single author
• Maximum of one entry per person allowed
• Maximum length of 1,500 words
• Entries must be in English
• Ideas should be clearly expressed at a college-educated, non-expert level
• All submissions are subject to Patexia's contest legal terms
• Failure to follow these rules may lead to disqualification from the contest