Patexia seeks evidence of commercial use of products and/or devices that describe a random access memory (RAM) units made exclusively of single-ported memory cells that can still conduct read/write operations within a single system’s clock cycle. The evidence of use may include, but is not limited to, references such as white papers, datasheets, product manuals, websites and journal reviews.

A benefit of dual-ported RAM is its ability to allow for a read and write operation to happen during every clock cycle. This benefit is particularly useful for several applications, such as video memory when a graphics processing unit (GPU) is drawing an image and writing it to memory, while the video hardware is reading the same image from the same memory and displaying it to a screen. However, despite these advantages, dual-ported RAM takes up significantly more chip space than its single-port RAM counterpart. As devices trend to smaller and thinner form factors, an ability to have the same advantages of a dual-ported RAM without its requisite space becomes increasingly important.

The technology described here is able to mimic dual-ported RAM functionality of allowing read and write operations to occur during a single system’s clock cycle using only single-ported RAM components. The method described accomplishes this by speeding up the read and write operations individually, as well as allowing parts of each to occur in parallel. The method follows the following broad steps:

• During the first step, the RAM unit determines if it’s reading and/or writing during the current clock cycle, and queues the read operation by preparing the bitlines for reading and determining the read address
• During the next step, the sense amplifier reads the data
• During the next step, the sense amplifier prepares the data for output, while the RAM unit simultaneously queues the write operation by preparing the bitlines for writing and determining the write address
• During the final step, the write driver writes the data, while the read data is simultaneously maintained for output

Overview of the RAM Unit’s Read/Write Operation

Qualifying Questions

1. Does the reference describe a random access memory (RAM) unit with single-ported memory cells that matches the following questions? And if “yes,” what is the name of the product?
2. Is the described product currently commercially used (e.g. imported, manufactured, etc.) in the United States? And if “yes,” what is the name of the entity that is doing so?
3. Was the reference published after January 1st, 2004?

Product Feature Questions

4. Is the product a RAM unit composed exclusively of single-ported memory cells?
5. Is the RAM unit configured to allow the single-ported memory cells to run read and write operations during a single system’s clock cycle? If “yes,” how does the RAM unit allow both read and write to occur during a single clock cycle?
6. Does the RAM unit achieve single clock cycle read/write by having part of the read operation happening concurrently with the write operation? If “yes,” what portions happen concurrently?
7. Does the RAM unit include control logic circuitry that controls the internal timing of the read operation, the write operation, the sense amplifier, and the write driver?

Rules and Submission Guidelines

Submissions for this Contest should include multiple references and products. References must contain examples of currently commercially utilized products and give technical details that describe either an exact match or functional equivalent to the feature described in the questions.