Patexia seeks prior art for US Patent 5,915,109 (US ‘109), with a focus on claim 15. The patent allegedly describes a microprocessor with an instruction set specifically designed for saturation operations.

This instruction set includes an ability where:

• each instruction is allowed to have an independent saturation value
• and the saturation value for each instruction is allowed to be completely different from the saturation values for other instruction in the same set

Saturation operations are computer operations where the results are limited to a fixed width, called the “saturation value.” US ‘109 describes this as typically occurring when an overflow has occurred as an operation result of an operation circuit, such as during video code processing based on MPEG2.

Typically, this saturation value is fixed for the entire architecture, making it difficult to perform any saturation operation for data having optional bit length in one instruction or for conventional microprocessors to provide convenient multimedia instructions capable of processing saturation operations at a high rate.

As such, Patexia seeks prior art that specifically describes:

• a saturation instruction operation, operating within an instruction set
• the saturation instruction operation allowing for multiple use cases (such as multimedia decoding) and not limited to saturating math instructions
• and the saturation instruction defining its own variable saturation value

Several of the known references (including US 5,448,509, US 5,684,728, US 5,508,951, and US 4,945,507, and US 5,559,973) were excluded specifically because they either:

• detail saturating math instructions, for example saturating to a variable value, but the value is based on the bit width of the operands and not on a field in the instruction
• or detail saturate instructions that saturate to a fixed value