
A Michael Chambers
Examiner (ID: 17983)
| Most Active Art Unit | 3407 |
| Art Unit(s) | 3401, 2899, 3727, 2103, 3753, 3407 |
| Total Applications | 3455 |
| Issued Applications | 3109 |
| Pending Applications | 98 |
| Abandoned Applications | 248 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15803981
[patent_doc_number] => 20200125133
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-23
[patent_title] => CLOCK PERIOD TUNING METHOD FOR RC CLOCK CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 16/502655
[patent_app_country] => US
[patent_app_date] => 2019-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7614
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502655
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/502655 | Clock period tuning method for RC clock circuits | Jul 2, 2019 | Issued |
Array
(
[id] => 16767244
[patent_doc_number] => 10979036
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-04-13
[patent_title] => Divider circuit
[patent_app_type] => utility
[patent_app_number] => 16/456298
[patent_app_country] => US
[patent_app_date] => 2019-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 3866
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456298
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/456298 | Divider circuit | Jun 27, 2019 | Issued |
Array
(
[id] => 16534938
[patent_doc_number] => 10877537
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-29
[patent_title] => Managing electrical power delivery to a peripheral device in a vehicle
[patent_app_type] => utility
[patent_app_number] => 16/448783
[patent_app_country] => US
[patent_app_date] => 2019-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 13937
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448783
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/448783 | Managing electrical power delivery to a peripheral device in a vehicle | Jun 20, 2019 | Issued |
Array
(
[id] => 16357188
[patent_doc_number] => 10797710
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-06
[patent_title] => Clock generator and method for generating clock signal
[patent_app_type] => utility
[patent_app_number] => 16/438406
[patent_app_country] => US
[patent_app_date] => 2019-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4057
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16438406
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/438406 | Clock generator and method for generating clock signal | Jun 10, 2019 | Issued |
Array
(
[id] => 15824289
[patent_doc_number] => 10637348
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-04-28
[patent_title] => Dead-time control for half-bridge driver circuit
[patent_app_type] => utility
[patent_app_number] => 16/436409
[patent_app_country] => US
[patent_app_date] => 2019-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7848
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436409
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/436409 | Dead-time control for half-bridge driver circuit | Jun 9, 2019 | Issued |
Array
(
[id] => 15271229
[patent_doc_number] => 20190384349
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => SYSTEM AND METHOD FOR A HYBRID CURRENT-MODE AND VOLTAGE-MODE INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 16/436130
[patent_app_country] => US
[patent_app_date] => 2019-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6078
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436130
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/436130 | System and method for a hybrid current-mode and voltage-mode integrated circuit | Jun 9, 2019 | Issued |
Array
(
[id] => 15775181
[patent_doc_number] => 20200118608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => APPARATUSES AND METHODS FOR PROVIDING VOLTAGES TO CONDUCTIVE LINES BETWEEN WHICH CLOCK SIGNAL LINES ARE DISPOSED
[patent_app_type] => utility
[patent_app_number] => 16/436655
[patent_app_country] => US
[patent_app_date] => 2019-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8029
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436655
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/436655 | Apparatus and methods for providing voltages to conductive lines between which clock signal lines are disposed | Jun 9, 2019 | Issued |
Array
(
[id] => 16464632
[patent_doc_number] => 10847997
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-11-24
[patent_title] => Wireless power transfer through low-e window
[patent_app_type] => utility
[patent_app_number] => 16/435228
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6042
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435228
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/435228 | Wireless power transfer through low-e window | Jun 6, 2019 | Issued |
Array
(
[id] => 15824569
[patent_doc_number] => 10637488
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-04-28
[patent_title] => Phase detection circuit, and clock generation circuit and semiconductor apparatus including the phase detection circuit
[patent_app_type] => utility
[patent_app_number] => 16/434660
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 9381
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16434660
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/434660 | Phase detection circuit, and clock generation circuit and semiconductor apparatus including the phase detection circuit | Jun 6, 2019 | Issued |
Array
(
[id] => 16133723
[patent_doc_number] => 10700640
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Harmonic-based nonlinearity factorization scheme to facilitate up-conversion mixer linearity
[patent_app_type] => utility
[patent_app_number] => 16/432668
[patent_app_country] => US
[patent_app_date] => 2019-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 3473
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432668
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/432668 | Harmonic-based nonlinearity factorization scheme to facilitate up-conversion mixer linearity | Jun 4, 2019 | Issued |
Array
(
[id] => 15208529
[patent_doc_number] => 20190366951
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-05
[patent_title] => ELECTRICAL POWER SYSTEM FOR A VEHICLE
[patent_app_type] => utility
[patent_app_number] => 16/431382
[patent_app_country] => US
[patent_app_date] => 2019-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7536
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431382
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/431382 | Electrical power system for a vehicle | Jun 3, 2019 | Issued |
Array
(
[id] => 14874675
[patent_doc_number] => 20190287579
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-19
[patent_title] => Sense Amplifier Constructions
[patent_app_type] => utility
[patent_app_number] => 16/429510
[patent_app_country] => US
[patent_app_date] => 2019-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4429
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429510
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/429510 | Sense amplifier constructions | Jun 2, 2019 | Issued |
Array
(
[id] => 15824517
[patent_doc_number] => 10637462
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-04-28
[patent_title] => System and method for SoC power-up sequencing
[patent_app_type] => utility
[patent_app_number] => 16/426985
[patent_app_country] => US
[patent_app_date] => 2019-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8914
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16426985
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/426985 | System and method for SoC power-up sequencing | May 29, 2019 | Issued |
Array
(
[id] => 16486624
[patent_doc_number] => 20200380231
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-03
[patent_title] => Signal processing circuit and related method of processing sensing signal
[patent_app_type] => utility
[patent_app_number] => 16/425887
[patent_app_country] => US
[patent_app_date] => 2019-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8049
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16425887
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/425887 | Signal processing circuit and related method of processing sensing signal | May 28, 2019 | Issued |
Array
(
[id] => 15747067
[patent_doc_number] => 20200112423
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-09
[patent_title] => QUADRATURE SIGNAL GENERATION
[patent_app_type] => utility
[patent_app_number] => 16/424743
[patent_app_country] => US
[patent_app_date] => 2019-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5743
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424743
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/424743 | Quadrature signal generation | May 28, 2019 | Issued |
Array
(
[id] => 16496294
[patent_doc_number] => 10862351
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Method and apparatus for performing communication in wireless power transmission system
[patent_app_type] => utility
[patent_app_number] => 16/422610
[patent_app_country] => US
[patent_app_date] => 2019-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 20203
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422610
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/422610 | Method and apparatus for performing communication in wireless power transmission system | May 23, 2019 | Issued |
Array
(
[id] => 15704877
[patent_doc_number] => 10608631
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-31
[patent_title] => Bridge output circuit, motor driver device and semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/416612
[patent_app_country] => US
[patent_app_date] => 2019-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 31
[patent_no_of_words] => 28177
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 349
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416612
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/416612 | Bridge output circuit, motor driver device and semiconductor device | May 19, 2019 | Issued |
Array
(
[id] => 15186243
[patent_doc_number] => 20190363713
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => INPUT DEVICE, CONTROL METHOD OF INPUT DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/416277
[patent_app_country] => US
[patent_app_date] => 2019-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3301
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416277
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/416277 | INPUT DEVICE, CONTROL METHOD OF INPUT DEVICE | May 19, 2019 | Abandoned |
Array
(
[id] => 14940249
[patent_doc_number] => 20190305763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => RANDOM NUMBER GENERATOR, RANDOM NUMBER GENERATION DEVICE, NEUROMORPHIC COMPUTER, AND QUANTUM COMPUTER
[patent_app_type] => utility
[patent_app_number] => 16/414838
[patent_app_country] => US
[patent_app_date] => 2019-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7666
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414838
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/414838 | Random number generator, random number generation device, neuromorphic computer, and quantum computer | May 16, 2019 | Issued |
Array
(
[id] => 15520737
[patent_doc_number] => 10566975
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-02-18
[patent_title] => Level translator for SPMI bus
[patent_app_type] => utility
[patent_app_number] => 16/412329
[patent_app_country] => US
[patent_app_date] => 2019-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5363
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412329
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/412329 | Level translator for SPMI bus | May 13, 2019 | Issued |