Search

Aaron A. Dehne

Examiner (ID: 8209, Phone: (571)270-7880 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
4116, 2829
Total Applications
304
Issued Applications
225
Pending Applications
0
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11339673 [patent_doc_number] => 20160365429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'PATTERNING OF VERTICAL NANOWIRE TRANSISOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 15/247826 [patent_app_country] => US [patent_app_date] => 2016-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6368 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15247826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/247826
Patterning of vertical nanowire transistor channel and gate with directed self assembly Aug 24, 2016 Issued
Array ( [id] => 11585913 [patent_doc_number] => 09640565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'GOA unit, method for manufacturing GOA unit, display substrate and display device' [patent_app_type] => utility [patent_app_number] => 15/154311 [patent_app_country] => US [patent_app_date] => 2016-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3820 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15154311 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/154311
GOA unit, method for manufacturing GOA unit, display substrate and display device May 12, 2016 Issued
Array ( [id] => 11028904 [patent_doc_number] => 20160225860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'Vertical Ferroelectric Field Effect Transistor Constructions, Constructions Comprising A Pair Of Vertical Ferroelectric Field Effect Transistors, Vertical Strings Of Ferroelectric Field Effect Transistors, And Vertical Strings Of Laterally Opposing Pairs Of Vertical Ferroelectric Field Effect Transistors' [patent_app_type] => utility [patent_app_number] => 15/095211 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095211 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095211
Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors Apr 10, 2016 Issued
Array ( [id] => 11753590 [patent_doc_number] => 09711611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Modified self-aligned contact process and semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/083383 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083383
Modified self-aligned contact process and semiconductor device Mar 28, 2016 Issued
Array ( [id] => 11000041 [patent_doc_number] => 20160196988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME' [patent_app_type] => utility [patent_app_number] => 15/070968 [patent_app_country] => US [patent_app_date] => 2016-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6879 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15070968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/070968
Embedded semiconductive chips in reconstituted wafers, and systems containing same Mar 14, 2016 Issued
Array ( [id] => 10787568 [patent_doc_number] => 20160133724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 14/997458 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6335 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997458 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/997458
Patterning of vertical nanowire transistor channel and gate with directed self assembly Jan 14, 2016 Issued
Array ( [id] => 11539673 [patent_doc_number] => 09614090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Semiconductor device and method of manufacturing the semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/984284 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 22226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984284 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/984284
Semiconductor device and method of manufacturing the semiconductor device Dec 29, 2015 Issued
Array ( [id] => 11732993 [patent_doc_number] => 20170194436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'FIN FIELD-EFFECT TRANSISTOR (FINFET) WITH REDUCED PARASITIC CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 14/984201 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5719 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984201 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/984201
Fin field-effect transistor (FinFET) with reduced parasitic capacitance Dec 29, 2015 Issued
Array ( [id] => 11321713 [patent_doc_number] => 09520462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-13 [patent_title] => 'Semiconductor device having capacitor integrated therein' [patent_app_type] => utility [patent_app_number] => 14/948942 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3654 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948942 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948942
Semiconductor device having capacitor integrated therein Nov 22, 2015 Issued
Array ( [id] => 11417593 [patent_doc_number] => 09564426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/931991 [patent_app_country] => US [patent_app_date] => 2015-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 10129 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14931991 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/931991
Semiconductor device and method of manufacturing the same Nov 3, 2015 Issued
Array ( [id] => 10780182 [patent_doc_number] => 20160126338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'TRANSISTOR AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/920193 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920193 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920193
Transistor and fabrication method thereof Oct 21, 2015 Issued
Array ( [id] => 10791333 [patent_doc_number] => 20160137489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'MICROELECTROMECHANICAL SYSTEMS DEVICE' [patent_app_type] => utility [patent_app_number] => 14/920184 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4077 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920184 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920184
MICROELECTROMECHANICAL SYSTEMS DEVICE Oct 21, 2015 Abandoned
Array ( [id] => 10758714 [patent_doc_number] => 20160104866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'PACKAGING STRUCTURE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL' [patent_app_type] => utility [patent_app_number] => 14/879153 [patent_app_country] => US [patent_app_date] => 2015-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879153 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/879153
PACKAGING STRUCTURE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL Oct 8, 2015 Abandoned
Array ( [id] => 11194314 [patent_doc_number] => 09425132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Stacked synchronous buck converter having chip embedded in outside recess of leadframe' [patent_app_type] => utility [patent_app_number] => 14/878408 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5341 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878408 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/878408
Stacked synchronous buck converter having chip embedded in outside recess of leadframe Oct 7, 2015 Issued
Array ( [id] => 10674042 [patent_doc_number] => 20160020188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'SELECTIVE DIE ELECTRICAL INSULATION BY ADDITIVE PROCESS' [patent_app_type] => utility [patent_app_number] => 14/868090 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12198 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/868090
Selective die electrical insulation by additive process Sep 27, 2015 Issued
Array ( [id] => 11898359 [patent_doc_number] => 09768301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Short channel effect suppression' [patent_app_type] => utility [patent_app_number] => 14/857610 [patent_app_country] => US [patent_app_date] => 2015-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 10064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14857610 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/857610
Short channel effect suppression Sep 16, 2015 Issued
Array ( [id] => 11307745 [patent_doc_number] => 09515151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Gettering agents in memory charge storage structures' [patent_app_type] => utility [patent_app_number] => 14/822272 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 5 [patent_no_of_words] => 6416 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822272 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/822272
Gettering agents in memory charge storage structures Aug 9, 2015 Issued
Array ( [id] => 10385367 [patent_doc_number] => 20150270374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 14/733925 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733925
Patterning of vertical nanowire transistor channel and gate with directed self assembly Jun 7, 2015 Issued
Array ( [id] => 10551425 [patent_doc_number] => 09276058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Methods of manufacturing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/732260 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 7816 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732260 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732260
Methods of manufacturing semiconductor devices Jun 4, 2015 Issued
Array ( [id] => 10370661 [patent_doc_number] => 20150255666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'MONOLITHIC INTEGRATION OF HETEROJUNCTION SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 14/718916 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7580 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718916 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/718916
Monolithic integration of heterojunction solar cells May 20, 2015 Issued
Menu