Search

Aaron M. Dunwoody

Examiner (ID: 16977, Phone: (571)272-7080 , Office: P/3679 )

Most Active Art Unit
3679
Art Unit(s)
3679, 3629
Total Applications
2740
Issued Applications
1948
Pending Applications
171
Abandoned Applications
657

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7780736 [patent_doc_number] => 20120042292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'METHOD OF SYNTHESIS OF AN ELECTRONIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/853627 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3369 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042292.pdf [firstpage_image] =>[orig_patent_app_number] => 12853627 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/853627
METHOD OF SYNTHESIS OF AN ELECTRONIC CIRCUIT Aug 9, 2010 Abandoned
Array ( [id] => 8763398 [patent_doc_number] => 08423937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Support program, design support device, and design support method' [patent_app_type] => utility [patent_app_number] => 12/849337 [patent_app_country] => US [patent_app_date] => 2010-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7260 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12849337 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/849337
Support program, design support device, and design support method Aug 2, 2010 Issued
Array ( [id] => 9707533 [patent_doc_number] => 08832629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Method for optimising cell variant selection within a design process for an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 13/811400 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5407 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13811400 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/811400
Method for optimising cell variant selection within a design process for an integrated circuit device Jul 22, 2010 Issued
Array ( [id] => 6519188 [patent_doc_number] => 20100286976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'Systems and Methods for Logic Verification' [patent_app_type] => utility [patent_app_number] => 12/840543 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3886 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20100286976.pdf [firstpage_image] =>[orig_patent_app_number] => 12840543 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840543
Systems and methods for logic verification Jul 20, 2010 Issued
Array ( [id] => 4511483 [patent_doc_number] => 07949969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Designing an ASIC based on execution of a software program on a processing system' [patent_app_type] => utility [patent_app_number] => 12/837767 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949969.pdf [firstpage_image] =>[orig_patent_app_number] => 12837767 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/837767
Designing an ASIC based on execution of a software program on a processing system Jul 15, 2010 Issued
Array ( [id] => 8001363 [patent_doc_number] => 08082529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Method and system for mapping a boolean logic network to a limited set of application-domain specific logic cells' [patent_app_type] => utility [patent_app_number] => 12/835675 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4448 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082529.pdf [firstpage_image] =>[orig_patent_app_number] => 12835675 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/835675
Method and system for mapping a boolean logic network to a limited set of application-domain specific logic cells Jul 12, 2010 Issued
Array ( [id] => 6596326 [patent_doc_number] => 20100275178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'COMPUTATIONAL EFFICIENCY IN PHOTOLITHOGRAPHIC PROCESS' [patent_app_type] => utility [patent_app_number] => 12/834502 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13260 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20100275178.pdf [firstpage_image] =>[orig_patent_app_number] => 12834502 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834502
Computational efficiency in photolithographic process simulation Jul 11, 2010 Issued
Array ( [id] => 6596272 [patent_doc_number] => 20100275174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/801895 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7253 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20100275174.pdf [firstpage_image] =>[orig_patent_app_number] => 12801895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801895
Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method Jun 29, 2010 Abandoned
Array ( [id] => 9869861 [patent_doc_number] => 08957636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Vehicle battery-pack equalization system and vehicle battery-pack equalization method' [patent_app_type] => utility [patent_app_number] => 13/575238 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6196 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13575238 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/575238
Vehicle battery-pack equalization system and vehicle battery-pack equalization method Jun 8, 2010 Issued
Array ( [id] => 8366781 [patent_doc_number] => 08255862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'System and method for analyzing temperature rise of a printed circuit board' [patent_app_type] => utility [patent_app_number] => 12/790857 [patent_app_country] => US [patent_app_date] => 2010-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2056 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12790857 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/790857
System and method for analyzing temperature rise of a printed circuit board May 30, 2010 Issued
Array ( [id] => 6415438 [patent_doc_number] => 20100306721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'WRITE ERROR VERIFICATION METHOD OF WRITING APPARATUS AND CREATION APPARATUS OF WRITE ERROR VERIFICATION DATA FOR WRITING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/787907 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11257 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306721.pdf [firstpage_image] =>[orig_patent_app_number] => 12787907 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787907
Write error verification method of writing apparatus and creation apparatus of write error verification data for writing apparatus May 25, 2010 Issued
Array ( [id] => 7569407 [patent_doc_number] => 20110289470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'Methods and Systems to Meet Technology Pattern Density Requirements of Semiconductor Fabrication Processes' [patent_app_type] => utility [patent_app_number] => 12/782337 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289470.pdf [firstpage_image] =>[orig_patent_app_number] => 12782337 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782337
Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes May 17, 2010 Issued
Array ( [id] => 8581023 [patent_doc_number] => 08347255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Equation based retargeting of design layouts' [patent_app_type] => utility [patent_app_number] => 12/782407 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12782407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782407
Equation based retargeting of design layouts May 17, 2010 Issued
Array ( [id] => 8591834 [patent_doc_number] => 08349709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Method of layout of pattern' [patent_app_type] => utility [patent_app_number] => 12/782217 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4948 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12782217 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782217
Method of layout of pattern May 17, 2010 Issued
Array ( [id] => 6566087 [patent_doc_number] => 20100223583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS' [patent_app_type] => utility [patent_app_number] => 12/777226 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5466 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223583.pdf [firstpage_image] =>[orig_patent_app_number] => 12777226 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/777226
Hierarchical feature extraction for electrical interaction calculations May 9, 2010 Issued
Array ( [id] => 7563096 [patent_doc_number] => 20110276930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'Minimizing Memory Array Representations for Enhanced Synthesis and Verification' [patent_app_type] => utility [patent_app_number] => 12/775607 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276930.pdf [firstpage_image] =>[orig_patent_app_number] => 12775607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775607
Minimizing memory array representations for enhanced synthesis and verification May 6, 2010 Issued
Array ( [id] => 6537373 [patent_doc_number] => 20100287524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION' [patent_app_type] => utility [patent_app_number] => 12/773462 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20753 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287524.pdf [firstpage_image] =>[orig_patent_app_number] => 12773462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773462
Metastability effects simulation for a circuit description May 3, 2010 Issued
Array ( [id] => 6497985 [patent_doc_number] => 20100209829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'PHOTOMASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/770062 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3560 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20100209829.pdf [firstpage_image] =>[orig_patent_app_number] => 12770062 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/770062
Photomask manufacturing method and semiconductor device manufacturing method Apr 28, 2010 Issued
Array ( [id] => 6519170 [patent_doc_number] => 20100286975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'Reliability Simulation Method and System' [patent_app_type] => utility [patent_app_number] => 12/754535 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 18315 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20100286975.pdf [firstpage_image] =>[orig_patent_app_number] => 12754535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754535
Reliability simulation method and system Apr 4, 2010 Issued
Array ( [id] => 8763391 [patent_doc_number] => 08423930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Area and power saving standard cell methodology' [patent_app_type] => utility [patent_app_number] => 12/754074 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3511 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754074 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754074
Area and power saving standard cell methodology Apr 4, 2010 Issued
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