
Abbigale A. Boyle
Examiner (ID: 701, Phone: (571)270-7919 , Office: P/2816 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2899, 2816, 2891 |
| Total Applications | 425 |
| Issued Applications | 231 |
| Pending Applications | 62 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16637915
[patent_doc_number] => 10916430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-09
[patent_title] => Semiconductor device and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 15/654110
[patent_app_country] => US
[patent_app_date] => 2017-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 73
[patent_no_of_words] => 37136
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654110
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/654110 | Semiconductor device and method for manufacturing the same | Jul 18, 2017 | Issued |
Array
(
[id] => 12141068
[patent_doc_number] => 20180019150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-18
[patent_title] => 'METHOD FOR PROCESSING ONE SEMICONDUCTOR WAFER OR A PLURALITY OF SEMICONDUCTOR WAFERS AND PROTECTIVE COVER FOR COVERING THE SEMICONDUCTOR WAFER'
[patent_app_type] => utility
[patent_app_number] => 15/648543
[patent_app_country] => US
[patent_app_date] => 2017-07-13
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648543
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/648543 | Method for processing one semiconductor wafer or a plurality of semiconductor wafers and protective cover for covering the semiconductor wafer | Jul 12, 2017 | Issued |
Array
(
[id] => 15547619
[patent_doc_number] => 10573600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-25
[patent_title] => Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
[patent_app_type] => utility
[patent_app_number] => 15/649491
[patent_app_country] => US
[patent_app_date] => 2017-07-13
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 18431643
[patent_doc_number] => 11676873
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Semiconductor package having sealant bridge
[patent_app_type] => utility
[patent_app_number] => 16/614765
[patent_app_country] => US
[patent_app_date] => 2017-06-30
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 16/614765 | Semiconductor package having sealant bridge | Jun 29, 2017 | Issued |
Array
(
[id] => 11990253
[patent_doc_number] => 20170294409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-12
[patent_title] => 'Multi-Chip Fan Out Package and Methods of Forming the Same'
[patent_app_type] => utility
[patent_app_number] => 15/632774
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[patent_app_date] => 2017-06-26
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/632774 | Multi-chip fan out package and methods of forming the same | Jun 25, 2017 | Issued |
Array
(
[id] => 12005450
[patent_doc_number] => 20170309605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-26
[patent_title] => 'ASSEMBLY OF WAFER STACKS'
[patent_app_type] => utility
[patent_app_number] => 15/626699
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/626699 | Assembly of wafer stacks | Jun 18, 2017 | Issued |
Array
(
[id] => 15234187
[patent_doc_number] => 10504823
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-10
[patent_title] => Power semiconductor device with small contact footprint and the preparation method
[patent_app_type] => utility
[patent_app_number] => 15/458797
[patent_app_country] => US
[patent_app_date] => 2017-03-14
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/458797 | Power semiconductor device with small contact footprint and the preparation method | Mar 13, 2017 | Issued |
Array
(
[id] => 11710602
[patent_doc_number] => 20170179101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'BRIDGE STRUCTURE FOR EMBEDDING SEMICONDUCTOR DIE'
[patent_app_type] => utility
[patent_app_number] => 15/446930
[patent_app_country] => US
[patent_app_date] => 2017-03-01
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/446930 | BRIDGE STRUCTURE FOR EMBEDDING SEMICONDUCTOR DIE | Feb 28, 2017 | Abandoned |
Array
(
[id] => 11652853
[patent_doc_number] => 20170148754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING'
[patent_app_type] => utility
[patent_app_number] => 15/421737
[patent_app_country] => US
[patent_app_date] => 2017-02-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/421737 | Extrusion-resistant solder interconnect structures and methods of forming | Jan 31, 2017 | Issued |
Array
(
[id] => 11623053
[patent_doc_number] => 20170133240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-11
[patent_title] => 'Silicon Heat-Dissipation Package For Compact Electronic Devices'
[patent_app_type] => utility
[patent_app_number] => 15/410620
[patent_app_country] => US
[patent_app_date] => 2017-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/410620 | Silicon Heat-Dissipation Package For Compact Electronic Devices | Jan 18, 2017 | Abandoned |
Array
(
[id] => 15388779
[patent_doc_number] => 10535588
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-14
[patent_title] => Die with metallized sidewall and method of manufacturing
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/408979 | Die with metallized sidewall and method of manufacturing | Jan 17, 2017 | Issued |
Array
(
[id] => 11824829
[patent_doc_number] => 20170213766
[patent_country] => US
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[patent_issue_date] => 2017-07-27
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME'
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Array
(
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Array
(
[id] => 11544797
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[patent_title] => 'SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME'
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Array
(
[id] => 11840133
[patent_doc_number] => 20170221853
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[patent_title] => 'ELECTRODE TERMINAL, SEMICONDUCTOR DEVICE, AND POWER CONVERSION APPARATUS'
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Array
(
[id] => 12631443
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[patent_kind] => A1
[patent_issue_date] => 2018-04-12
[patent_title] => SEMICONDUCTOR PACKAGE UTILIZING EMBEDDED BRIDGE THROUGH-SILICON-VIA INTERCONNECT COMPONENT
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/286582 | Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods | Oct 5, 2016 | Issued |
Array
(
[id] => 11959371
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/286844 | Wafer-level chip-size package with redistribution layer | Oct 5, 2016 | Issued |
Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/286253 | Fan-out semiconductor package and manufacturing method thereof | Oct 4, 2016 | Issued |