Abbigale A. Boyle

Array ( [id] => 12195617 [patent_doc_number] => 09899353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Off-chip vias in stacked chips' [patent_app_type] => utility [patent_app_number] => 14/725975 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6817 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14725975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11424878 [patent_doc_number] => 20170033024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'Method For Mounting An Electrical Component In Which A Hood Is Used, And A Hood That Is Suitable For Use In This Method' [patent_app_type] => utility [patent_app_number] => 15/301772 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6026 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15301772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10472282 [patent_doc_number] => 20150357298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/637545 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10802706 [patent_doc_number] => 20160148863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'NON-CONTIGUOUS DUMMY STRUCTURE SURROUNDING THROUGH-SUBSTRATE VIA NEAR INTEGRATED CIRCUIT WIRES' [patent_app_type] => utility [patent_app_number] => 14/549846 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12355035 [patent_doc_number] => 09953857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Semiconductor device with buried local interconnects [patent_app_type] => utility [patent_app_number] => 14/548648 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 3381 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14548648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16973560 [patent_doc_number] => 11069540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Package on package and a method of fabricating the same [patent_app_type] => utility [patent_app_number] => 14/547717 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 3399 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10270250 [patent_doc_number] => 20150155247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'BRIDGE STRUCTURE FOR EMBEDDING SEMICONDUCTOR DIE' [patent_app_type] => utility [patent_app_number] => 14/546734 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10795078 [patent_doc_number] => 20160141235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'PRINTED CIRCUIT BOARD ASSEMBLY WITH IMAGE SENSOR MOUNTED THEREON' [patent_app_type] => utility [patent_app_number] => 14/543936 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2816 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10370421 [patent_doc_number] => 20150255426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SEMICONDUCTOR DEVICE WITH REDUCED WARPAGE' [patent_app_type] => utility [patent_app_number] => 14/546484 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12109034 [patent_doc_number] => 09865522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Composite heat sink structures' [patent_app_type] => utility [patent_app_number] => 14/546136 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 11488 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10795077 [patent_doc_number] => 20160141234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'INTEGRATED DEVICE PACKAGE COMPRISING SILICON BRIDGE IN PHOTO IMAGEABLE LAYER' [patent_app_type] => utility [patent_app_number] => 14/543560 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14601 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10294597 [patent_doc_number] => 20150179596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/543105 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3415 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10294554 [patent_doc_number] => 20150179553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'PRE-MOLDED INTEGRATED CIRCUIT PACKAGES' [patent_app_type] => utility [patent_app_number] => 14/536962 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14536962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16048021 [patent_doc_number] => 10685894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semi-conductor module with an encapsulating cement mass that covers a semi-conductor component [patent_app_type] => utility [patent_app_number] => 15/034626 [patent_app_country] => US [patent_app_date] => 2014-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2037 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15034626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9857954 [patent_doc_number] => 20150037971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'CHIP CONNECTION STRUCTURE AND METHOD OF FORMING' [patent_app_type] => utility [patent_app_number] => 14/510426 [patent_app_country] => US [patent_app_date] => 2014-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2658 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14510426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10213199 [patent_doc_number] => 20150098191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'Silicon Heat-Dissipation Package For Compact Electronic Devices' [patent_app_type] => utility [patent_app_number] => 14/507779 [patent_app_country] => US [patent_app_date] => 2014-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11711 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14507779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10909461 [patent_doc_number] => 20140312477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'Lead And Lead Frame For Power Package' [patent_app_type] => utility [patent_app_number] => 14/320644 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3471 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10479377 [patent_doc_number] => 20150364394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'Method for Building Up a Fan-Out RDL Structure with Fine Pitch Line-Width and Line-Spacing' [patent_app_type] => utility [patent_app_number] => 14/305640 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13549 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10479356 [patent_doc_number] => 20150364373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'Quad Flat No Lead Package And Method Of Making' [patent_app_type] => utility [patent_app_number] => 14/301942 [patent_app_country] => US [patent_app_date] => 2014-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14301942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10472252 [patent_doc_number] => 20150357268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'POWER SEMICONDUCTOR DEVICE WITH SMALL CONTACT FOOTPRINT AND THE PREPARATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/298892 [patent_app_country] => US [patent_app_date] => 2014-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5588 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14298892 [rel_patent_id] =>[rel_patent_doc_number] =>)