Search

Abbigale A. Boyle

Examiner (ID: 701, Phone: (571)270-7919 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2816, 2891
Total Applications
425
Issued Applications
231
Pending Applications
62
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6058978 [patent_doc_number] => 20110198749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'Semiconductor chip package and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/929783 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3623 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20110198749.pdf [firstpage_image] =>[orig_patent_app_number] => 12929783 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929783
Semiconductor chip package and method of manufacturing the same Feb 14, 2011 Abandoned
Array ( [id] => 5944236 [patent_doc_number] => 20110104856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE/POST HEAT SPREADER' [patent_app_type] => utility [patent_app_number] => 13/004881 [patent_app_country] => US [patent_app_date] => 2011-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 32887 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20110104856.pdf [firstpage_image] =>[orig_patent_app_number] => 13004881 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/004881
Method of making a semiconductor chip assembly with a post/base/post heat spreader Jan 11, 2011 Issued
Array ( [id] => 5940790 [patent_doc_number] => 20110101410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE/POST HEAT SPREADER' [patent_app_type] => utility [patent_app_number] => 12/987166 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 32887 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20110101410.pdf [firstpage_image] =>[orig_patent_app_number] => 12987166 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/987166
Semiconductor chip assembly with post/base/post heat spreader Jan 9, 2011 Issued
Array ( [id] => 10158587 [patent_doc_number] => 09190371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Self-organizing network with chip package having multiple interconnection configurations' [patent_app_type] => utility [patent_app_number] => 12/974165 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4466 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12974165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/974165
Self-organizing network with chip package having multiple interconnection configurations Dec 20, 2010 Issued
Array ( [id] => 8249162 [patent_doc_number] => 20120153483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'BARRIERLESS SINGLE-PHASE INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 12/973281 [patent_app_country] => US [patent_app_date] => 2010-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153483.pdf [firstpage_image] =>[orig_patent_app_number] => 12973281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/973281
BARRIERLESS SINGLE-PHASE INTERCONNECT Dec 19, 2010 Abandoned
Array ( [id] => 8250622 [patent_doc_number] => 20120154945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'OPTICAL APERTURES AND APPLICATIONS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/970680 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7122 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20120154945.pdf [firstpage_image] =>[orig_patent_app_number] => 12970680 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970680
OPTICAL APERTURES AND APPLICATIONS THEREOF Dec 15, 2010 Abandoned
Array ( [id] => 8235898 [patent_doc_number] => 20120144634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'METAL OXIDE VARISTOR DESIGN AND ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 12/968063 [patent_app_country] => US [patent_app_date] => 2010-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 751 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12968063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/968063
METAL OXIDE VARISTOR DESIGN AND ASSEMBLY Dec 13, 2010 Abandoned
Array ( [id] => 8435442 [patent_doc_number] => 08283211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Method of making a semiconductor chip assembly with a bump/base heat spreader and a dual-angle cavity in the bump' [patent_app_type] => utility [patent_app_number] => 12/951066 [patent_app_country] => US [patent_app_date] => 2010-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 67 [patent_no_of_words] => 31000 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12951066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/951066
Method of making a semiconductor chip assembly with a bump/base heat spreader and a dual-angle cavity in the bump Nov 21, 2010 Issued
Array ( [id] => 5929415 [patent_doc_number] => 20110039374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-17 [patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A CAVITY IN THE BUMP' [patent_app_type] => utility [patent_app_number] => 12/913762 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 29241 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20110039374.pdf [firstpage_image] =>[orig_patent_app_number] => 12913762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913762
METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A CAVITY IN THE BUMP Oct 27, 2010 Abandoned
Array ( [id] => 8249141 [patent_doc_number] => 20120153461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'SEMICONDUCTOR COMPONENT, SEMICONDUCTOR WAFER COMPONENT, MANUFACTURING METHOD OF SEMICONDUCTOR COMPONENT, AND MANUFACTURING METHOD OF JOINING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/263900 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6938 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153461.pdf [firstpage_image] =>[orig_patent_app_number] => 13263900 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/263900
SEMICONDUCTOR COMPONENT, SEMICONDUCTOR WAFER COMPONENT, MANUFACTURING METHOD OF SEMICONDUCTOR COMPONENT, AND MANUFACTURING METHOD OF JOINING STRUCTURE Jul 19, 2010 Abandoned
Array ( [id] => 7577405 [patent_doc_number] => 20110291287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 12/786931 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5727 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291287.pdf [firstpage_image] =>[orig_patent_app_number] => 12786931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786931
THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE May 24, 2010 Abandoned
Array ( [id] => 6375275 [patent_doc_number] => 20100301366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'ORGANIC ELECTRO-LUMINESCENCE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/786944 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301366.pdf [firstpage_image] =>[orig_patent_app_number] => 12786944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786944
ORGANIC ELECTRO-LUMINESCENCE DEVICE May 24, 2010 Abandoned
Array ( [id] => 6376213 [patent_doc_number] => 20100301495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 12/786871 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5345 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301495.pdf [firstpage_image] =>[orig_patent_app_number] => 12786871 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786871
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME May 24, 2010 Abandoned
Array ( [id] => 7564904 [patent_doc_number] => 20110284967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'Stressed Fin-FET Devices with Low Contact Resistance' [patent_app_type] => utility [patent_app_number] => 12/786397 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4282 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20110284967.pdf [firstpage_image] =>[orig_patent_app_number] => 12786397 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786397
Stressed Fin-FET devices with low contact resistance May 23, 2010 Issued
Array ( [id] => 7564886 [patent_doc_number] => 20110284949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'VERTICAL TRANSISTOR AND A METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/786343 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20110284949.pdf [firstpage_image] =>[orig_patent_app_number] => 12786343 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786343
VERTICAL TRANSISTOR AND A METHOD OF FABRICATING THE SAME May 23, 2010 Abandoned
Array ( [id] => 6376162 [patent_doc_number] => 20100301486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'HIGH-ASPECT RATIO CONTACT ELEMENT WITH SUPERIOR SHAPE IN A SEMICONDUCTOR DEVICE FOR IMPROVING LINER DEPOSITION' [patent_app_type] => utility [patent_app_number] => 12/785726 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301486.pdf [firstpage_image] =>[orig_patent_app_number] => 12785726 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/785726
HIGH-ASPECT RATIO CONTACT ELEMENT WITH SUPERIOR SHAPE IN A SEMICONDUCTOR DEVICE FOR IMPROVING LINER DEPOSITION May 23, 2010 Abandoned
Array ( [id] => 6052311 [patent_doc_number] => 20110108936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'PRESSURE DETECTOR AND PRESSURE DETECTOR ARRAY' [patent_app_type] => utility [patent_app_number] => 12/785998 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5018 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20110108936.pdf [firstpage_image] =>[orig_patent_app_number] => 12785998 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/785998
Pressure detector and pressure detector array May 23, 2010 Issued
Array ( [id] => 10537804 [patent_doc_number] => 09263439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'III-nitride switching device with an emulated diode' [patent_app_type] => utility [patent_app_number] => 12/800902 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3066 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12800902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/800902
III-nitride switching device with an emulated diode May 23, 2010 Issued
Array ( [id] => 6376210 [patent_doc_number] => 20100301494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'RE-ESTABLISHING A HYDROPHOBIC SURFACE OF SENSITIVE LOW-K DIELECTRICS IN MICROSTRUCTURE DEVICES' [patent_app_type] => utility [patent_app_number] => 12/786117 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7280 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301494.pdf [firstpage_image] =>[orig_patent_app_number] => 12786117 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786117
RE-ESTABLISHING A HYDROPHOBIC SURFACE OF SENSITIVE LOW-K DIELECTRICS IN MICROSTRUCTURE DEVICES May 23, 2010 Abandoned
Array ( [id] => 8328517 [patent_doc_number] => 08236613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Wafer level chip scale package method using clip array' [patent_app_type] => utility [patent_app_number] => 12/786328 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3347 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12786328 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786328
Wafer level chip scale package method using clip array May 23, 2010 Issued
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