
Abbigale A. Boyle
Examiner (ID: 701, Phone: (571)270-7919 , Office: P/2816 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2899, 2816, 2891 |
| Total Applications | 425 |
| Issued Applications | 231 |
| Pending Applications | 62 |
| Abandoned Applications | 141 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6058978
[patent_doc_number] => 20110198749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-18
[patent_title] => 'Semiconductor chip package and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/929783
[patent_app_country] => US
[patent_app_date] => 2011-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3623
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0198/20110198749.pdf
[firstpage_image] =>[orig_patent_app_number] => 12929783
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/929783 | Semiconductor chip package and method of manufacturing the same | Feb 14, 2011 | Abandoned |
Array
(
[id] => 5944236
[patent_doc_number] => 20110104856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-05
[patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/BASE/POST HEAT SPREADER'
[patent_app_type] => utility
[patent_app_number] => 13/004881
[patent_app_country] => US
[patent_app_date] => 2011-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 39
[patent_no_of_words] => 32887
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20110104856.pdf
[firstpage_image] =>[orig_patent_app_number] => 13004881
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/004881 | Method of making a semiconductor chip assembly with a post/base/post heat spreader | Jan 11, 2011 | Issued |
Array
(
[id] => 5940790
[patent_doc_number] => 20110101410
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-05
[patent_title] => 'SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE/POST HEAT SPREADER'
[patent_app_type] => utility
[patent_app_number] => 12/987166
[patent_app_country] => US
[patent_app_date] => 2011-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
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[patent_no_of_words] => 32887
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20110101410.pdf
[firstpage_image] =>[orig_patent_app_number] => 12987166
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/987166 | Semiconductor chip assembly with post/base/post heat spreader | Jan 9, 2011 | Issued |
Array
(
[id] => 10158587
[patent_doc_number] => 09190371
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-17
[patent_title] => 'Self-organizing network with chip package having multiple interconnection configurations'
[patent_app_type] => utility
[patent_app_number] => 12/974165
[patent_app_country] => US
[patent_app_date] => 2010-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 4466
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12974165
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/974165 | Self-organizing network with chip package having multiple interconnection configurations | Dec 20, 2010 | Issued |
Array
(
[id] => 8249162
[patent_doc_number] => 20120153483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-21
[patent_title] => 'BARRIERLESS SINGLE-PHASE INTERCONNECT'
[patent_app_type] => utility
[patent_app_number] => 12/973281
[patent_app_country] => US
[patent_app_date] => 2010-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2814
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20120153483.pdf
[firstpage_image] =>[orig_patent_app_number] => 12973281
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/973281 | BARRIERLESS SINGLE-PHASE INTERCONNECT | Dec 19, 2010 | Abandoned |
Array
(
[id] => 8250622
[patent_doc_number] => 20120154945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-21
[patent_title] => 'OPTICAL APERTURES AND APPLICATIONS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/970680
[patent_app_country] => US
[patent_app_date] => 2010-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 7122
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0154/20120154945.pdf
[firstpage_image] =>[orig_patent_app_number] => 12970680
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/970680 | OPTICAL APERTURES AND APPLICATIONS THEREOF | Dec 15, 2010 | Abandoned |
Array
(
[id] => 8235898
[patent_doc_number] => 20120144634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-14
[patent_title] => 'METAL OXIDE VARISTOR DESIGN AND ASSEMBLY'
[patent_app_type] => utility
[patent_app_number] => 12/968063
[patent_app_country] => US
[patent_app_date] => 2010-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 751
[patent_no_of_claims] => 15
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12968063
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/968063 | METAL OXIDE VARISTOR DESIGN AND ASSEMBLY | Dec 13, 2010 | Abandoned |
Array
(
[id] => 8435442
[patent_doc_number] => 08283211
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-09
[patent_title] => 'Method of making a semiconductor chip assembly with a bump/base heat spreader and a dual-angle cavity in the bump'
[patent_app_type] => utility
[patent_app_number] => 12/951066
[patent_app_country] => US
[patent_app_date] => 2010-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 49
[patent_figures_cnt] => 67
[patent_no_of_words] => 31000
[patent_no_of_claims] => 15
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[patent_words_short_claim] => 246
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12951066
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/951066 | Method of making a semiconductor chip assembly with a bump/base heat spreader and a dual-angle cavity in the bump | Nov 21, 2010 | Issued |
Array
(
[id] => 5929415
[patent_doc_number] => 20110039374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-17
[patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A CAVITY IN THE BUMP'
[patent_app_type] => utility
[patent_app_number] => 12/913762
[patent_app_country] => US
[patent_app_date] => 2010-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
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[pdf_file] => publications/A1/0039/20110039374.pdf
[firstpage_image] =>[orig_patent_app_number] => 12913762
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/913762 | METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A CAVITY IN THE BUMP | Oct 27, 2010 | Abandoned |
Array
(
[id] => 8249141
[patent_doc_number] => 20120153461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-21
[patent_title] => 'SEMICONDUCTOR COMPONENT, SEMICONDUCTOR WAFER COMPONENT, MANUFACTURING METHOD OF SEMICONDUCTOR COMPONENT, AND MANUFACTURING METHOD OF JOINING STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 13/263900
[patent_app_country] => US
[patent_app_date] => 2010-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0153/20120153461.pdf
[firstpage_image] =>[orig_patent_app_number] => 13263900
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/263900 | SEMICONDUCTOR COMPONENT, SEMICONDUCTOR WAFER COMPONENT, MANUFACTURING METHOD OF SEMICONDUCTOR COMPONENT, AND MANUFACTURING METHOD OF JOINING STRUCTURE | Jul 19, 2010 | Abandoned |
Array
(
[id] => 7577405
[patent_doc_number] => 20110291287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-01
[patent_title] => 'THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE'
[patent_app_type] => utility
[patent_app_number] => 12/786931
[patent_app_country] => US
[patent_app_date] => 2010-05-25
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[firstpage_image] =>[orig_patent_app_number] => 12786931
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/786931 | THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE | May 24, 2010 | Abandoned |
Array
(
[id] => 6375275
[patent_doc_number] => 20100301366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-02
[patent_title] => 'ORGANIC ELECTRO-LUMINESCENCE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/786944
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/786944 | ORGANIC ELECTRO-LUMINESCENCE DEVICE | May 24, 2010 | Abandoned |
Array
(
[id] => 6376213
[patent_doc_number] => 20100301495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-02
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/786871 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME | May 24, 2010 | Abandoned |
Array
(
[id] => 7564904
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[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-24
[patent_title] => 'Stressed Fin-FET Devices with Low Contact Resistance'
[patent_app_type] => utility
[patent_app_number] => 12/786397
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/786397 | Stressed Fin-FET devices with low contact resistance | May 23, 2010 | Issued |
Array
(
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Array
(
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[patent_title] => 'HIGH-ASPECT RATIO CONTACT ELEMENT WITH SUPERIOR SHAPE IN A SEMICONDUCTOR DEVICE FOR IMPROVING LINER DEPOSITION'
[patent_app_type] => utility
[patent_app_number] => 12/785726
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Array
(
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[patent_title] => 'PRESSURE DETECTOR AND PRESSURE DETECTOR ARRAY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/785998 | Pressure detector and pressure detector array | May 23, 2010 | Issued |
Array
(
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Array
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Array
(
[id] => 8328517
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[patent_title] => 'Wafer level chip scale package method using clip array'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/786328 | Wafer level chip scale package method using clip array | May 23, 2010 | Issued |