Search

Abbigale A. Boyle

Examiner (ID: 701, Phone: (571)270-7919 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2816, 2891
Total Applications
425
Issued Applications
231
Pending Applications
62
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16888941 [patent_doc_number] => 20210175138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Semiconductors Having Die Pads with Environmental Protection and Process of Making Semiconductors Having Die Pads with Environmental Protection [patent_app_type] => utility [patent_app_number] => 16/704644 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704644
Semiconductors Having Die Pads with Environmental Protection and Process of Making Semiconductors Having Die Pads with Environmental Protection Dec 4, 2019 Pending
Array ( [id] => 17559126 [patent_doc_number] => 11315848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Semiconductor device and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/703037 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 52 [patent_no_of_words] => 19504 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703037 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703037
Semiconductor device and method of manufacturing semiconductor device Dec 3, 2019 Issued
Array ( [id] => 16020915 [patent_doc_number] => 20200185301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => Semiconductor Package, Metal Sheet for Use in a Semiconductor Package, and Method for Producing a Semiconductor Package [patent_app_type] => utility [patent_app_number] => 16/701251 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701251 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/701251
Semiconductor package, metal sheet for use in a semiconductor package, and method for producing a semiconductor package Dec 2, 2019 Issued
Array ( [id] => 17210709 [patent_doc_number] => 11171086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/700485 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8050 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/700485
Semiconductor device Dec 1, 2019 Issued
Array ( [id] => 18235983 [patent_doc_number] => 11600547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Semiconductor package with expanded heat spreader [patent_app_type] => utility [patent_app_number] => 16/700361 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 6917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/700361
Semiconductor package with expanded heat spreader Dec 1, 2019 Issued
Array ( [id] => 18507573 [patent_doc_number] => 11705400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/699265 [patent_app_country] => US [patent_app_date] => 2019-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8053 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699265 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699265
Semiconductor package Nov 28, 2019 Issued
Array ( [id] => 16448322 [patent_doc_number] => 10840253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Increased gate coupling effect in multigate transistor [patent_app_type] => utility [patent_app_number] => 16/695445 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 9292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695445
Increased gate coupling effect in multigate transistor Nov 25, 2019 Issued
Array ( [id] => 17574144 [patent_doc_number] => 11322418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Assembly of stacked elements and method of producing the same [patent_app_type] => utility [patent_app_number] => 16/685141 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4138 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685141
Assembly of stacked elements and method of producing the same Nov 14, 2019 Issued
Array ( [id] => 18031976 [patent_doc_number] => 11515174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Semiconductor devices with package-level compartmental shielding and associated systems and methods [patent_app_type] => utility [patent_app_number] => 16/681214 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3236 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681214
Semiconductor devices with package-level compartmental shielding and associated systems and methods Nov 11, 2019 Issued
Array ( [id] => 15905975 [patent_doc_number] => 20200152508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => METHOD FOR CONTACTING A BURIED INTERCONNECT RAIL OF AN INTEGRATED CIRCUIT CHIP FROM THE BACK SIDE OF THE IC [patent_app_type] => utility [patent_app_number] => 16/675080 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675080 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675080
Method for contacting a buried interconnect rail of an integrated circuit chip from the back side of the IC Nov 4, 2019 Issued
Array ( [id] => 18704733 [patent_doc_number] => 11791250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Lead frame, semiconductor device, and lead frame manufacturing method [patent_app_type] => utility [patent_app_number] => 16/668078 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 5970 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16668078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/668078
Lead frame, semiconductor device, and lead frame manufacturing method Oct 29, 2019 Issued
Array ( [id] => 16731136 [patent_doc_number] => 20210098284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => FULLY ALIGNED TOP VIAS WITH REPLACEMENT METAL LINES [patent_app_type] => utility [patent_app_number] => 16/585412 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585412
Fully aligned top vias with replacement metal lines Sep 26, 2019 Issued
Array ( [id] => 17107442 [patent_doc_number] => 11127668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Semiconductor device and method of forming double-sided fan-out wafer level package [patent_app_type] => utility [patent_app_number] => 16/570049 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 6462 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570049 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570049
Semiconductor device and method of forming double-sided fan-out wafer level package Sep 12, 2019 Issued
Array ( [id] => 17047940 [patent_doc_number] => 11101130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Method of filling grooves and holes in a substrate [patent_app_type] => utility [patent_app_number] => 16/570408 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 7466 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570408 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570408
Method of filling grooves and holes in a substrate Sep 12, 2019 Issued
Array ( [id] => 17410295 [patent_doc_number] => 11251193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/558725 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 8216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558725 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558725
Semiconductor memory device Sep 2, 2019 Issued
Array ( [id] => 17986012 [patent_doc_number] => 20220352049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => POWER SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/621249 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17621249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/621249
Power semiconductor apparatus and method for manufacturing the same Aug 28, 2019 Issued
Array ( [id] => 17431717 [patent_doc_number] => 20220059426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD FOR PRODUCING A POWER MODULE UNIT, POWER MODULE UNIT, NETWORK PART AND FREQUENCY CONVERTER [patent_app_type] => utility [patent_app_number] => 17/275621 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17275621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/275621
METHOD FOR PRODUCING A POWER MODULE UNIT, POWER MODULE UNIT, NETWORK PART AND FREQUENCY CONVERTER Jul 2, 2019 Abandoned
Array ( [id] => 14938587 [patent_doc_number] => 20190304932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => GUARD RING METHOD FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/443663 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443663
Guard ring method for semiconductor devices Jun 16, 2019 Issued
Array ( [id] => 19597061 [patent_doc_number] => 12154915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/603733 [patent_app_country] => US [patent_app_date] => 2019-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17603733 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/603733
Display device Apr 16, 2019 Issued
Array ( [id] => 14413877 [patent_doc_number] => 20190172782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => PACKAGING SUBSTRATE FOR SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/269300 [patent_app_country] => US [patent_app_date] => 2019-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269300 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/269300
PACKAGING SUBSTRATE FOR SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND METHOD Feb 5, 2019 Abandoned
Menu