
Abbigale A. Boyle
Examiner (ID: 6386, Phone: (571)270-7919 , Office: P/2816 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2899, 2891, 2816 |
| Total Applications | 419 |
| Issued Applications | 231 |
| Pending Applications | 66 |
| Abandoned Applications | 139 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14969363
[patent_doc_number] => 20190312160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-10
[patent_title] => METHOD FOR MANUFACTURING FINGER ELECTRODE FOR SOLAR CELL AND FINGER ELECTRODE FOR SOLAR CELL PREPARED THEREBY
[patent_app_type] => utility
[patent_app_number] => 16/207519
[patent_app_country] => US
[patent_app_date] => 2018-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4910
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207519
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/207519 | METHOD FOR MANUFACTURING FINGER ELECTRODE FOR SOLAR CELL AND FINGER ELECTRODE FOR SOLAR CELL PREPARED THEREBY | Dec 2, 2018 | Abandoned |
Array
(
[id] => 17092828
[patent_doc_number] => 11121026
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Semiconductor device and method of manufacture
[patent_app_type] => utility
[patent_app_number] => 16/208213
[patent_app_country] => US
[patent_app_date] => 2018-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11144
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208213
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/208213 | Semiconductor device and method of manufacture | Dec 2, 2018 | Issued |
Array
(
[id] => 16000769
[patent_doc_number] => 20200176255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => METHODS OF FORMING SUBLITHOGRAPHIC FEATURES OF A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/208122
[patent_app_country] => US
[patent_app_date] => 2018-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6515
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208122
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/208122 | METHODS OF FORMING SUBLITHOGRAPHIC FEATURES OF A SEMICONDUCTOR DEVICE | Dec 2, 2018 | Abandoned |
Array
(
[id] => 14110229
[patent_doc_number] => 20190096790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => Dense Redistribution Layers in Semiconductor Packages and Methods of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 16/203705
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11558
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 15
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203705
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/203705 | Dense redistribution layers in semiconductor packages and methods of forming the same | Nov 28, 2018 | Issued |
Array
(
[id] => 17002721
[patent_doc_number] => 11081544
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-03
[patent_title] => Method of manufacturing a semiconductor device comprising first and second field stop zone portions
[patent_app_type] => utility
[patent_app_number] => 16/202752
[patent_app_country] => US
[patent_app_date] => 2018-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 8242
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202752
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/202752 | Method of manufacturing a semiconductor device comprising first and second field stop zone portions | Nov 27, 2018 | Issued |
Array
(
[id] => 16440386
[patent_doc_number] => 20200357713
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-12
[patent_title] => MANUFACTURING METHOD OF MOUNTING STRUCTURE, AND SHEET THEREFOR
[patent_app_type] => utility
[patent_app_number] => 16/760092
[patent_app_country] => US
[patent_app_date] => 2018-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7446
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16760092
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/760092 | Manufacturing method of mounting structure, and sheet therefor | Oct 29, 2018 | Issued |
Array
(
[id] => 15776037
[patent_doc_number] => 20200119036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => FORMING TERMINATIONS IN STACKED MEMORY ARRAYS
[patent_app_type] => utility
[patent_app_number] => 16/159955
[patent_app_country] => US
[patent_app_date] => 2018-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11031
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159955
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159955 | Forming terminations in stacked memory arrays | Oct 14, 2018 | Issued |
Array
(
[id] => 15775947
[patent_doc_number] => 20200118991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => PRE-PATTERNED FINE-PITCH BOND PAD INTERPOSER
[patent_app_type] => utility
[patent_app_number] => 16/160197
[patent_app_country] => US
[patent_app_date] => 2018-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4490
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160197
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/160197 | PRE-PATTERNED FINE-PITCH BOND PAD INTERPOSER | Oct 14, 2018 | Pending |
Array
(
[id] => 17941723
[patent_doc_number] => 11476182
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-18
[patent_title] => Assembly of flexible and integrated module packages with leadframes
[patent_app_type] => utility
[patent_app_number] => 16/605735
[patent_app_country] => US
[patent_app_date] => 2018-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7894
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605735
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/605735 | Assembly of flexible and integrated module packages with leadframes | Oct 7, 2018 | Issued |
Array
(
[id] => 15718187
[patent_doc_number] => 20200105861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => EMBEDDED PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 16/145111
[patent_app_country] => US
[patent_app_date] => 2018-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7805
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145111
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/145111 | Embedded precision resistor for non-planar semiconductor device architectures | Sep 26, 2018 | Issued |
Array
(
[id] => 15688123
[patent_doc_number] => 20200098725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => SEMICONDUCTOR PACKAGE OR SEMICONDUCTOR PACKAGE STRUCTURE WITH DUAL-SIDED INTERPOSER AND MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/143339
[patent_app_country] => US
[patent_app_date] => 2018-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9510
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143339
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/143339 | SEMICONDUCTOR PACKAGE OR SEMICONDUCTOR PACKAGE STRUCTURE WITH DUAL-SIDED INTERPOSER AND MEMORY | Sep 25, 2018 | Abandoned |
Array
(
[id] => 15688069
[patent_doc_number] => 20200098698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE PACKAGE (FCCSP), AND FAN OUT SHIELDING CONCEPTS
[patent_app_type] => utility
[patent_app_number] => 16/143212
[patent_app_country] => US
[patent_app_date] => 2018-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14456
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143212
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/143212 | NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE PACKAGE (FCCSP), AND FAN OUT SHIELDING CONCEPTS | Sep 25, 2018 | Abandoned |
Array
(
[id] => 15688021
[patent_doc_number] => 20200098674
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => PACKAGE EDGE MOUNTED FRAME STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/142249
[patent_app_country] => US
[patent_app_date] => 2018-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8193
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142249
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/142249 | PACKAGE EDGE MOUNTED FRAME STRUCTURES | Sep 25, 2018 | Abandoned |
Array
(
[id] => 15564429
[patent_doc_number] => 20200066626
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => POCKET STRUCTURES, MATERIALS, AND METHODS FOR INTEGRATED CIRCUIT PACKAGE SUPPORTS
[patent_app_type] => utility
[patent_app_number] => 16/107655
[patent_app_country] => US
[patent_app_date] => 2018-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10716
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107655
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/107655 | POCKET STRUCTURES, MATERIALS, AND METHODS FOR INTEGRATED CIRCUIT PACKAGE SUPPORTS | Aug 20, 2018 | Abandoned |
Array
(
[id] => 18735715
[patent_doc_number] => 11804456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Wirebond and leadframe magnetic inductors
[patent_app_type] => utility
[patent_app_number] => 16/107791
[patent_app_country] => US
[patent_app_date] => 2018-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 22
[patent_no_of_words] => 11397
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107791
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/107791 | Wirebond and leadframe magnetic inductors | Aug 20, 2018 | Issued |
Array
(
[id] => 13785387
[patent_doc_number] => 20190006232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
[patent_app_type] => utility
[patent_app_number] => 16/103372
[patent_app_country] => US
[patent_app_date] => 2018-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5520
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103372
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/103372 | Metallization lines on integrated circuit products | Aug 13, 2018 | Issued |
Array
(
[id] => 15462009
[patent_doc_number] => 20200043829
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-06
[patent_title] => THERMAL MANAGEMENT SOLUTIONS FOR STACKED INTEGRATED CIRCUIT DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/055428
[patent_app_country] => US
[patent_app_date] => 2018-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7062
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055428
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/055428 | THERMAL MANAGEMENT SOLUTIONS FOR STACKED INTEGRATED CIRCUIT DEVICES | Aug 5, 2018 | Abandoned |
Array
(
[id] => 13559043
[patent_doc_number] => 20180331069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-15
[patent_title] => Package Structure and Method of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 16/043435
[patent_app_country] => US
[patent_app_date] => 2018-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9750
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043435
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/043435 | Package structure and method of forming the same | Jul 23, 2018 | Issued |
Array
(
[id] => 15414811
[patent_doc_number] => 20200027728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-23
[patent_title] => SUBSTRATE PACKAGE WITH GLASS DIELECTRIC
[patent_app_type] => utility
[patent_app_number] => 16/042203
[patent_app_country] => US
[patent_app_date] => 2018-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8734
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16042203
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/042203 | SUBSTRATE PACKAGE WITH GLASS DIELECTRIC | Jul 22, 2018 | Abandoned |
Array
(
[id] => 18782206
[patent_doc_number] => 11823972
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-21
[patent_title] => Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices
[patent_app_type] => utility
[patent_app_number] => 16/040746
[patent_app_country] => US
[patent_app_date] => 2018-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 19
[patent_no_of_words] => 8274
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040746
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/040746 | Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices | Jul 19, 2018 | Issued |