Search

Abdellah Lamane

Examiner (ID: 583)

Most Active Art Unit
2611
Art Unit(s)
2611, 2635
Total Applications
2
Issued Applications
2
Pending Applications
0
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18379787 [patent_doc_number] => 20230154876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP [patent_app_type] => utility [patent_app_number] => 18/093880 [patent_app_country] => US [patent_app_date] => 2023-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093880
Semiconductor devices including a thick metal layer and a bump Jan 5, 2023 Issued
Array ( [id] => 18535464 [patent_doc_number] => 20230240547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => MULTI SENSOR RADIO FREQUENCY DETECTION [patent_app_type] => utility [patent_app_number] => 18/086172 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086172 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/086172
Multi sensor radio frequency detection Dec 20, 2022 Issued
Array ( [id] => 18967518 [patent_doc_number] => 11901299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Interconnect architecture with silicon interposer and EMIB [patent_app_type] => utility [patent_app_number] => 18/079753 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5476 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079753 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/079753
Interconnect architecture with silicon interposer and EMIB Dec 11, 2022 Issued
Array ( [id] => 18267481 [patent_doc_number] => 20230088723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE INCLUDING PROMOTERS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/071595 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/071595
Semiconductor device package including promoters and method of manufacturing the same Nov 28, 2022 Issued
Array ( [id] => 18782280 [patent_doc_number] => 11824047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Method for fabricating semiconductor device with stacked dies [patent_app_type] => utility [patent_app_number] => 17/993248 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10778 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17993248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/993248
Method for fabricating semiconductor device with stacked dies Nov 22, 2022 Issued
Array ( [id] => 18267068 [patent_doc_number] => 20230088310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/991694 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/991694
Semiconductor memory having memory cell regions and other regions alternately arranged along a bit line direction Nov 20, 2022 Issued
Array ( [id] => 18935503 [patent_doc_number] => 11887947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Electronic device including conductive element on side surface of substrate [patent_app_type] => utility [patent_app_number] => 17/974553 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 10062 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974553 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/974553
Electronic device including conductive element on side surface of substrate Oct 26, 2022 Issued
Array ( [id] => 18198291 [patent_doc_number] => 20230051810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => CHEMICAL BONDING METHOD, PACKAGE-TYPE ELECTRONIC COMPONENT, AND HYBRID BONDING METHOD FOR ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/962061 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962061
Chemical bonding method, package-type electronic component, and hybrid bonding method for electronic device Oct 6, 2022 Issued
Array ( [id] => 18141145 [patent_doc_number] => 20230014987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/946326 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946326
Semiconductor package Sep 15, 2022 Issued
Array ( [id] => 18891044 [patent_doc_number] => 11869821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Semiconductor package having molding layer with inclined side wall [patent_app_type] => utility [patent_app_number] => 17/879272 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 14586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879272
Semiconductor package having molding layer with inclined side wall Aug 1, 2022 Issued
Array ( [id] => 18040157 [patent_doc_number] => 20220384374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => Chiplets 3D SoIC System Integration and Fabrication Methods [patent_app_type] => utility [patent_app_number] => 17/815738 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815738
Chiplets 3D SoIC system integration and fabrication methods Jul 27, 2022 Issued
Array ( [id] => 18221734 [patent_doc_number] => 20230060728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SOC PMUT SUITABLE FOR HIGH-DENSITY SYSTEM INTEGRATION, ARRAY CHIP, AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/870810 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870810
SOC PMUT suitable for high-density system integration, array chip, and manufacturing method thereof Jul 20, 2022 Issued
Array ( [id] => 18639569 [patent_doc_number] => 11764192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Semiconductor package including underfill material layer and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/861580 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861580 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861580
Semiconductor package including underfill material layer and method of forming the same Jul 10, 2022 Issued
Array ( [id] => 19046733 [patent_doc_number] => 11935853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Memory devices with backside bond pads under a memory array [patent_app_type] => utility [patent_app_number] => 17/854428 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854428
Memory devices with backside bond pads under a memory array Jun 29, 2022 Issued
Array ( [id] => 17933302 [patent_doc_number] => 20220328428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MOISTURE BARRIER FOR BOND PADS AND INTEGRATED CIRCUIT HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/809257 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809257
Moisture barrier for bond pads and integrated circuit having the same Jun 26, 2022 Issued
Array ( [id] => 18112939 [patent_doc_number] => 20230005819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA (TSV) VERTICAL INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/841627 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841627 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841627
Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects Jun 14, 2022 Issued
Array ( [id] => 18797009 [patent_doc_number] => 11830844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/834923 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 17008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834923
Semiconductor structure Jun 6, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
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