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Abdullah Almamun

Examiner (ID: 8068, Phone: (571)270-3392 , Office: P/2431 )

Most Active Art Unit
2431
Art Unit(s)
2431
Total Applications
484
Issued Applications
363
Pending Applications
42
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20069985 [patent_doc_number] => 20250208207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => TEST (DFT) AND DESIGN FOR DEBUG (DFD) GATED POWER DOMAINS [patent_app_type] => utility [patent_app_number] => 18/395952 [patent_app_country] => US [patent_app_date] => 2023-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395952
TEST (DFT) AND DESIGN FOR DEBUG (DFD) GATED POWER DOMAINS Dec 25, 2023 Pending
Array ( [id] => 19834268 [patent_doc_number] => 20250086054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SYSTEMS AND METHODS FOR MEMORY RECOVERY USING SECONDARY MEMORY [patent_app_type] => utility [patent_app_number] => 18/511224 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511224 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511224
SYSTEMS AND METHODS FOR MEMORY RECOVERY USING SECONDARY MEMORY Nov 15, 2023 Pending
Array ( [id] => 18508093 [patent_doc_number] => 11705925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Dynamic bit flipping order for iterative error correction [patent_app_type] => utility [patent_app_number] => 17/899495 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899495
Dynamic bit flipping order for iterative error correction Aug 29, 2022 Issued
Array ( [id] => 18062615 [patent_doc_number] => 20220393702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => Decoding Signals By Guessing Noise [patent_app_type] => utility [patent_app_number] => 17/819697 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819697
Decoding signals by guessing noise Aug 14, 2022 Issued
Array ( [id] => 18038800 [patent_doc_number] => 20220383016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => ENHANCED MATRIX SYMBOL ERROR CORRECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/819057 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819057
Enhanced matrix symbol error correction method Aug 10, 2022 Issued
Array ( [id] => 18703379 [patent_doc_number] => 11789890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities [patent_app_type] => utility [patent_app_number] => 17/850927 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4513 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850927
Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities Jun 26, 2022 Issued
Array ( [id] => 17871818 [patent_doc_number] => 20220294555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => OPTIMIZING DELAY-SENSITIVE NETWORK-BASED COMMUNICATIONS WITH LATENCY GUIDANCE [patent_app_type] => utility [patent_app_number] => 17/804579 [patent_app_country] => US [patent_app_date] => 2022-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804579
OPTIMIZING DELAY-SENSITIVE NETWORK-BASED COMMUNICATIONS WITH LATENCY GUIDANCE May 29, 2022 Abandoned
Array ( [id] => 17796586 [patent_doc_number] => 20220255678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => CHAIN BROADCASTING IN VEHICLE-TO-EVERYTHING (V2X) COMMUNICATIONS [patent_app_type] => utility [patent_app_number] => 17/660649 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660649
CHAIN BROADCASTING IN VEHICLE-TO-EVERYTHING (V2X) COMMUNICATIONS Apr 25, 2022 Abandoned
Array ( [id] => 17853858 [patent_doc_number] => 20220283900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => METHODS AND SYSTEMS FOR RAID PROTECTION IN ZONED SOLID-STATE DRIVES [patent_app_type] => utility [patent_app_number] => 17/727511 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727511
Methods and systems for raid protection in zoned solid-state drives Apr 21, 2022 Issued
Array ( [id] => 17778681 [patent_doc_number] => 20220245031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/660332 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660332 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660332
Apparatuses, systems, and methods for error correction Apr 21, 2022 Issued
Array ( [id] => 18527776 [patent_doc_number] => 11714769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Continuous adaptive data capture optimization for interface circuits [patent_app_type] => utility [patent_app_number] => 17/724221 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 9513 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724221 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724221
Continuous adaptive data capture optimization for interface circuits Apr 18, 2022 Issued
Array ( [id] => 17736684 [patent_doc_number] => 20220222143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY INTEGRITY PERFORMANCE ENHANCEMENT SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/708984 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708984
MEMORY INTEGRITY PERFORMANCE ENHANCEMENT SYSTEMS AND METHODS Mar 29, 2022 Abandoned
Array ( [id] => 18592063 [patent_doc_number] => 11740961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-29 [patent_title] => Data recovery using dynamic segment ordering [patent_app_type] => utility [patent_app_number] => 17/701976 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701976 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701976
Data recovery using dynamic segment ordering Mar 22, 2022 Issued
Array ( [id] => 18480014 [patent_doc_number] => 11693754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates [patent_app_type] => utility [patent_app_number] => 17/685557 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 21060 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685557
Aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates Mar 2, 2022 Issued
Array ( [id] => 18493424 [patent_doc_number] => 11698841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Integrated circuit chip with cores asymmetrically oriented with respect to each other [patent_app_type] => utility [patent_app_number] => 17/585979 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4905 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585979 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585979
Integrated circuit chip with cores asymmetrically oriented with respect to each other Jan 26, 2022 Issued
Array ( [id] => 17736682 [patent_doc_number] => 20220222141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => GENERATING A BALANCED CODEWORD PROTECTED BY AN ERROR CORRECTION CODE [patent_app_type] => utility [patent_app_number] => 17/586501 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586501
Generating a balanced codeword protected by an error correction code Jan 26, 2022 Issued
Array ( [id] => 17600293 [patent_doc_number] => 20220149867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF [patent_app_type] => utility [patent_app_number] => 17/582635 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582635 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582635
Transmitter and method for generating additional parity thereof Jan 23, 2022 Issued
Array ( [id] => 17661693 [patent_doc_number] => 20220182158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => Margin Test Methods and Circuits [patent_app_type] => utility [patent_app_number] => 17/557518 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557518
Margin Test Methods and Circuits Dec 20, 2021 Abandoned
Array ( [id] => 17484431 [patent_doc_number] => 20220091935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => PROVIDING DATA OF A MEMORY SYSTEM BASED ON AN ADJUSTABLE ERROR RATE [patent_app_type] => utility [patent_app_number] => 17/544772 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544772 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544772
Providing data of a memory system based on an adjustable error rate Dec 6, 2021 Issued
Array ( [id] => 17475113 [patent_doc_number] => 20220082617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => DEVICE, SYSTEM AND METHOD TO SUPPORT COMMUNICATION OF TEST, DEBUG OR TRACE INFORMATION WITH AN EXTERNAL INPUT/OUTPUT INTERFACE [patent_app_type] => utility [patent_app_number] => 17/538482 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538482 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538482
Device, system and method to support communication of test, debug or trace information with an external input/output interface Nov 29, 2021 Issued
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