
Abigail Anne Risic
Examiner (ID: 15112, Phone: (571)270-7819 , Office: P/3671 )
| Most Active Art Unit | 3671 |
| Art Unit(s) | 3671 |
| Total Applications | 1386 |
| Issued Applications | 1012 |
| Pending Applications | 88 |
| Abandoned Applications | 315 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10758666
[patent_doc_number] => 20160104819
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-14
[patent_title] => 'METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP'
[patent_app_type] => utility
[patent_app_number] => 14/891658
[patent_app_country] => US
[patent_app_date] => 2014-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3347
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14891658
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/891658 | Method for producing an optoelectronic semiconductor chip | May 13, 2014 | Issued |
Array
(
[id] => 12256977
[patent_doc_number] => 09929126
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-27
[patent_title] => 'Packages with metal line crack prevention design'
[patent_app_type] => utility
[patent_app_number] => 14/244111
[patent_app_country] => US
[patent_app_date] => 2014-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 4643
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14244111
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/244111 | Packages with metal line crack prevention design | Apr 2, 2014 | Issued |
Array
(
[id] => 11453536
[patent_doc_number] => 09577191
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-21
[patent_title] => 'RRAM cell bottom electrode formation'
[patent_app_type] => utility
[patent_app_number] => 14/242983
[patent_app_country] => US
[patent_app_date] => 2014-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 5348
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242983
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242983 | RRAM cell bottom electrode formation | Apr 1, 2014 | Issued |
Array
(
[id] => 10400989
[patent_doc_number] => 20150285998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'INTEGRATION OF PHOTONIC, ELECTRONIC, AND SENSOR DEVICES WITH SOI VLSI MICROPROCESSOR TECHNOLOGY'
[patent_app_type] => utility
[patent_app_number] => 14/243436
[patent_app_country] => US
[patent_app_date] => 2014-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 12892
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243436
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/243436 | Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology | Apr 1, 2014 | Issued |
Array
(
[id] => 12375480
[patent_doc_number] => 09960052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-01
[patent_title] => Methods for etching a metal layer to form an interconnection structure for semiconductor applications
[patent_app_type] => utility
[patent_app_number] => 14/243677
[patent_app_country] => US
[patent_app_date] => 2014-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5446
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243677
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/243677 | Methods for etching a metal layer to form an interconnection structure for semiconductor applications | Apr 1, 2014 | Issued |
Array
(
[id] => 11687450
[patent_doc_number] => 09685501
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-20
[patent_title] => 'Low parasitic capacitance finFET device'
[patent_app_type] => utility
[patent_app_number] => 14/242907
[patent_app_country] => US
[patent_app_date] => 2014-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 5533
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242907
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242907 | Low parasitic capacitance finFET device | Apr 1, 2014 | Issued |
Array
(
[id] => 10402734
[patent_doc_number] => 20150287743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS'
[patent_app_type] => utility
[patent_app_number] => 14/243398
[patent_app_country] => US
[patent_app_date] => 2014-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7075
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243398
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/243398 | MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS | Apr 1, 2014 | Abandoned |
Array
(
[id] => 10151990
[patent_doc_number] => 09184290
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-10
[patent_title] => 'Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer'
[patent_app_type] => utility
[patent_app_number] => 14/242955
[patent_app_country] => US
[patent_app_date] => 2014-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 7314
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242955
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242955 | Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer | Apr 1, 2014 | Issued |
Array
(
[id] => 10394460
[patent_doc_number] => 20150279468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'COMPOSITE IMPURITY SCHEME FOR MEMORY TECHNOLOGIES'
[patent_app_type] => utility
[patent_app_number] => 14/242757
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5295
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242757
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242757 | Composite impurity scheme for memory technologies | Mar 31, 2014 | Issued |
Array
(
[id] => 10388730
[patent_doc_number] => 20150273737
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'FLEXIBLE AND STRETCHABLE GRAPHENE FILM AND PREPARING METHOD OF THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/242118
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8466
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242118
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242118 | FLEXIBLE AND STRETCHABLE GRAPHENE FILM AND PREPARING METHOD OF THE SAME | Mar 31, 2014 | Abandoned |
Array
(
[id] => 10394952
[patent_doc_number] => 20150279959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'METHODS OF REMOVING PORTIONS OF FINS BY PREFORMING A SELECTIVELY ETCHABLE MATERIAL IN THE SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 14/242529
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6145
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242529
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242529 | Methods of removing portions of fins by preforming a selectively etchable material in the substrate | Mar 31, 2014 | Issued |
Array
(
[id] => 10394721
[patent_doc_number] => 20150279728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'INTERCONNECT ETCH WITH POLYMER LAYER EDGE PROTECTION'
[patent_app_type] => utility
[patent_app_number] => 14/231997
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3753
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14231997
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/231997 | Interconnect etch with polymer layer edge protection | Mar 31, 2014 | Issued |
Array
(
[id] => 11453271
[patent_doc_number] => 09576923
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-21
[patent_title] => 'Semiconductor chip with patterned underbump metallization and polymer film'
[patent_app_type] => utility
[patent_app_number] => 14/242008
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 5792
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242008
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242008 | Semiconductor chip with patterned underbump metallization and polymer film | Mar 31, 2014 | Issued |
Array
(
[id] => 10394964
[patent_doc_number] => 20150279971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'METHODS OF FORMING FINS FOR FINFET SEMICONDUCTOR DEVICES AND THE SELECTIVE REMOVAL OF SUCH FINS'
[patent_app_type] => utility
[patent_app_number] => 14/242130
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6698
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242130
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242130 | Methods of forming fins for FinFET semiconductor devices and the selective removal of such fins | Mar 31, 2014 | Issued |
Array
(
[id] => 10518925
[patent_doc_number] => 09245980
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-26
[patent_title] => 'Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/242472
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 7797
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242472
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242472 | Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor device | Mar 31, 2014 | Issued |
Array
(
[id] => 12436353
[patent_doc_number] => 09978635
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-22
[patent_title] => Method and apparatus for semiconductor device with reduced device footprint
[patent_app_type] => utility
[patent_app_number] => 14/242269
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 45
[patent_no_of_words] => 8331
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242269
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242269 | Method and apparatus for semiconductor device with reduced device footprint | Mar 31, 2014 | Issued |
Array
(
[id] => 11636557
[patent_doc_number] => 09658523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-23
[patent_title] => 'Interconnect structure having large self-aligned vias'
[patent_app_type] => utility
[patent_app_number] => 14/231448
[patent_app_country] => US
[patent_app_date] => 2014-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 22
[patent_no_of_words] => 4627
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14231448
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/231448 | Interconnect structure having large self-aligned vias | Mar 30, 2014 | Issued |
Array
(
[id] => 10568425
[patent_doc_number] => 09291587
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-22
[patent_title] => 'Method for forming aligned patterns on a substrate'
[patent_app_type] => utility
[patent_app_number] => 14/230127
[patent_app_country] => US
[patent_app_date] => 2014-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 32
[patent_no_of_words] => 16431
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230127
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/230127 | Method for forming aligned patterns on a substrate | Mar 30, 2014 | Issued |
Array
(
[id] => 10285922
[patent_doc_number] => 20150170920
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'DOPANT ETCH SELECTIVITY CONTROL'
[patent_app_type] => utility
[patent_app_number] => 14/230590
[patent_app_country] => US
[patent_app_date] => 2014-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8631
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230590
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/230590 | Dopant etch selectivity control | Mar 30, 2014 | Issued |
Array
(
[id] => 10394963
[patent_doc_number] => 20150279970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'SOI FINFET TRANSISTOR WITH STRAINED CHANNEL'
[patent_app_type] => utility
[patent_app_number] => 14/231466
[patent_app_country] => US
[patent_app_date] => 2014-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6465
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14231466
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/231466 | SOI FinFET transistor with strained channel | Mar 30, 2014 | Issued |