Search

Abraham Bahta

Examiner (ID: 12090, Phone: (571)272-1532 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
1744, 1317, 2923, 1775, 1513, 1774, 2913
Total Applications
4784
Issued Applications
4535
Pending Applications
54
Abandoned Applications
200

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19189985 [patent_doc_number] => 20240168898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => DISTRIBUTED QUEUE MULTI-BUS ON MULTI-CPU CHIPS [patent_app_type] => utility [patent_app_number] => 18/487176 [patent_app_country] => US [patent_app_date] => 2023-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18487176 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/487176
Distributed queue multi-bus on multi-CPU chips Oct 15, 2023 Issued
Array ( [id] => 19963807 [patent_doc_number] => 12333316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Self-managed configuration of information technology assets in an information technology environment [patent_app_type] => utility [patent_app_number] => 18/483619 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483619
Self-managed configuration of information technology assets in an information technology environment Oct 9, 2023 Issued
Array ( [id] => 18896979 [patent_doc_number] => 20240012464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Very Low Power Microcontroller System [patent_app_type] => utility [patent_app_number] => 18/474510 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474510 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/474510
Very Low Power Microcontroller System Sep 25, 2023 Pending
Array ( [id] => 19925173 [patent_doc_number] => 12299459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Pipeline configuration support [patent_app_type] => utility [patent_app_number] => 18/367744 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18367744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/367744
Pipeline configuration support Sep 12, 2023 Issued
Array ( [id] => 19819031 [patent_doc_number] => 20250077238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => PRE-APPROVAL-BASED MACHINE CONFIGURATION [patent_app_type] => utility [patent_app_number] => 18/241489 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18241489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/241489
PRE-APPROVAL-BASED MACHINE CONFIGURATION Aug 31, 2023 Pending
Array ( [id] => 20176318 [patent_doc_number] => 12395078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Control method and apparatus, and electronic device [patent_app_type] => utility [patent_app_number] => 18/240720 [patent_app_country] => US [patent_app_date] => 2023-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5067 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240720 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240720
Control method and apparatus, and electronic device Aug 30, 2023 Issued
Array ( [id] => 19911536 [patent_doc_number] => 12287745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Direct memory access architecture with multi-level multi-striding [patent_app_type] => utility [patent_app_number] => 18/229616 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229616
Direct memory access architecture with multi-level multi-striding Aug 1, 2023 Issued
Array ( [id] => 19756497 [patent_doc_number] => 20250045062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => OUT-OF-BAND (OOB) SETTINGS MANAGEMENT IN HETEROGENEOUS COMPUTING PLATFORMS [patent_app_type] => utility [patent_app_number] => 18/364111 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364111
Out-of-Band (OOB) settings management in heterogeneous computing platforms Aug 1, 2023 Issued
Array ( [id] => 18787934 [patent_doc_number] => 20230376318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => DISTRIBUTED GEOMETRY [patent_app_type] => utility [patent_app_number] => 18/363333 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363333
Distributed geometry Jul 31, 2023 Issued
Array ( [id] => 19747856 [patent_doc_number] => 20250036421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SYSTEM AND METHOD FOR BOOT AND SHUTDOWN SYNCHRONIZATION OF SERVER OPERATING SYSTEM AND COMPONENT OPERATING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/359555 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359555
System and method for boot and shutdown synchronization of server operating system and component operating system Jul 25, 2023 Issued
Array ( [id] => 19685972 [patent_doc_number] => 20250004517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SYSTEM AND METHOD FOR OPTIMIZING BILL OF MATERIAL COST AND POWER PERFORMANCE OF PLATFORM SYSTEM-ON-CHIP FOR BATTERY MANAGEMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 18/357417 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357417 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357417
System and method for optimizing bill of material cost and power performance of platform system-on-chip for battery management system Jul 23, 2023 Issued
Array ( [id] => 20145704 [patent_doc_number] => 12380047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Expanded data link width for main band chip module connection in alternate modes [patent_app_type] => utility [patent_app_number] => 18/352600 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7379 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352600
Expanded data link width for main band chip module connection in alternate modes Jul 13, 2023 Issued
Array ( [id] => 18960077 [patent_doc_number] => 20240048404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => ELECTRONIC DEVICE, CORRESPONDING BUS COMMUNICATION SYSTEM AND METHOD OF CONFIGURING A BUS COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/350345 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350345
Electronic device, corresponding bus communication system and method of configuring a bus communication system Jul 10, 2023 Issued
Array ( [id] => 19949831 [patent_doc_number] => 12321193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-03 [patent_title] => Hierarchically-aware buffering for clock structures [patent_app_type] => utility [patent_app_number] => 18/347315 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 1091 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347315 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347315
Hierarchically-aware buffering for clock structures Jul 4, 2023 Issued
Array ( [id] => 19686428 [patent_doc_number] => 20250004973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => NETWORK CONNECTIVITY FOR OUT-OF-BAND PROCESSORS IN HETEROGENEOUS COMPUTING PLATFORMS [patent_app_type] => utility [patent_app_number] => 18/344940 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344940
Network connectivity for out-of-band processors in heterogeneous computing platforms Jun 29, 2023 Issued
Array ( [id] => 19949938 [patent_doc_number] => 12321300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Apparatus and methods for translating transactions between one or more requesting units and a target unit [patent_app_type] => utility [patent_app_number] => 18/345992 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345992
Apparatus and methods for translating transactions between one or more requesting units and a target unit Jun 29, 2023 Issued
Array ( [id] => 19685990 [patent_doc_number] => 20250004535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => OPTIMIZED POWER MANAGEMENT FOR COMPUTER SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/344102 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344102 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344102
Optimized power management for computer systems Jun 28, 2023 Issued
Array ( [id] => 20145398 [patent_doc_number] => 12379740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Technique to mitigate clock generation failure at high input clock slew [patent_app_type] => utility [patent_app_number] => 18/344087 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344087 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344087
Technique to mitigate clock generation failure at high input clock slew Jun 28, 2023 Issued
Array ( [id] => 18925099 [patent_doc_number] => 20240028103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => Mechanism for Saving Power on a Bus Interface [patent_app_type] => utility [patent_app_number] => 18/337189 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337189
Mechanism for Saving Power on a Bus Interface Jun 18, 2023 Issued
Array ( [id] => 19617380 [patent_doc_number] => 20240403060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => REBOOTING OR HALTING A HUNG NODE WITHIN CLUSTERED COMPUTER ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/327670 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327670
REBOOTING OR HALTING A HUNG NODE WITHIN CLUSTERED COMPUTER ENVIRONMENT May 31, 2023 Pending
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