
Abu Z. Ghaffari
Examiner (ID: 4367, Phone: (571)270-3799 , Office: P/2195 )
| Most Active Art Unit | 2195 |
| Art Unit(s) | 2195 |
| Total Applications | 723 |
| Issued Applications | 520 |
| Pending Applications | 72 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1431429
[patent_doc_number] => 06519684
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Low overhead method for selecting and updating an entry in a cache memory'
[patent_app_type] => B1
[patent_app_number] => 09/447254
[patent_app_country] => US
[patent_app_date] => 1999-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3965
[patent_no_of_claims] => 20
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/519/06519684.pdf
[firstpage_image] =>[orig_patent_app_number] => 09447254
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/447254 | Low overhead method for selecting and updating an entry in a cache memory | Nov 22, 1999 | Issued |
Array
(
[id] => 1311345
[patent_doc_number] => 06625708
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-23
[patent_title] => 'Method and apparatus for dynamically defining line buffer configurations'
[patent_app_type] => B1
[patent_app_number] => 09/447536
[patent_app_country] => US
[patent_app_date] => 1999-11-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/625/06625708.pdf
[firstpage_image] =>[orig_patent_app_number] => 09447536
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/447536 | Method and apparatus for dynamically defining line buffer configurations | Nov 22, 1999 | Issued |
Array
(
[id] => 1329105
[patent_doc_number] => 06606687
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-12
[patent_title] => 'Optimized hardware cleaning function for VIVT data cache'
[patent_app_type] => B1
[patent_app_number] => 09/447194
[patent_app_country] => US
[patent_app_date] => 1999-11-22
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[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/606/06606687.pdf
[firstpage_image] =>[orig_patent_app_number] => 09447194
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/447194 | Optimized hardware cleaning function for VIVT data cache | Nov 21, 1999 | Issued |
Array
(
[id] => 1206886
[patent_doc_number] => 06721859
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-13
[patent_title] => 'Multi-protocol media storage device implementing protocols optimized for storing and retrieving both asynchronous and isochronous data'
[patent_app_type] => B1
[patent_app_number] => 09/422870
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/721/06721859.pdf
[firstpage_image] =>[orig_patent_app_number] => 09422870
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/422870 | Multi-protocol media storage device implementing protocols optimized for storing and retrieving both asynchronous and isochronous data | Oct 20, 1999 | Issued |
Array
(
[id] => 1429289
[patent_doc_number] => 06530001
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-04
[patent_title] => 'Computer system controlling memory clock signal and method for controlling the same'
[patent_app_type] => B1
[patent_app_number] => 09/419774
[patent_app_country] => US
[patent_app_date] => 1999-10-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/530/06530001.pdf
[firstpage_image] =>[orig_patent_app_number] => 09419774
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/419774 | Computer system controlling memory clock signal and method for controlling the same | Oct 17, 1999 | Issued |
Array
(
[id] => 4391526
[patent_doc_number] => 06289413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Cached synchronous DRAM architecture having a mode register programmable cache policy'
[patent_app_type] => 1
[patent_app_number] => 9/360373
[patent_app_country] => US
[patent_app_date] => 1999-10-15
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[pdf_file] => patents/06/289/06289413.pdf
[firstpage_image] =>[orig_patent_app_number] => 360373
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/360373 | Cached synchronous DRAM architecture having a mode register programmable cache policy | Oct 14, 1999 | Issued |
Array
(
[id] => 1584619
[patent_doc_number] => 06449665
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Means for reducing direct memory access'
[patent_app_type] => B1
[patent_app_number] => 09/419690
[patent_app_country] => US
[patent_app_date] => 1999-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/06/449/06449665.pdf
[firstpage_image] =>[orig_patent_app_number] => 09419690
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/419690 | Means for reducing direct memory access | Oct 13, 1999 | Issued |
Array
(
[id] => 1236319
[patent_doc_number] => 06694422
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-17
[patent_title] => 'Semiconductor memory device having adjustable page length and page depth'
[patent_app_type] => B1
[patent_app_number] => 09/419711
[patent_app_country] => US
[patent_app_date] => 1999-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/694/06694422.pdf
[firstpage_image] =>[orig_patent_app_number] => 09419711
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/419711 | Semiconductor memory device having adjustable page length and page depth | Oct 13, 1999 | Issued |
| 09/418184 | SYSTEM AND METHOD FOR ASSIGNING RATINGS TO MUTUAL FUNDS AND OTHER INVESTMENT FUNDS BASED ON THE VALUE OF VARIOUS FUTURE AND OPTION SECURITIES | Oct 11, 1999 | Abandoned |
Array
(
[id] => 1557258
[patent_doc_number] => 06349365
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'User-prioritized cache replacement'
[patent_app_type] => B1
[patent_app_number] => 09/415892
[patent_app_country] => US
[patent_app_date] => 1999-10-08
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[pdf_file] => patents/06/349/06349365.pdf
[firstpage_image] =>[orig_patent_app_number] => 09415892
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/415892 | User-prioritized cache replacement | Oct 7, 1999 | Issued |
Array
(
[id] => 1567456
[patent_doc_number] => 06363464
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Redundant processor controlled system'
[patent_app_type] => B1
[patent_app_number] => 09/414915
[patent_app_country] => US
[patent_app_date] => 1999-10-08
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09414915
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/414915 | Redundant processor controlled system | Oct 7, 1999 | Issued |
Array
(
[id] => 1484966
[patent_doc_number] => 06453387
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[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Fully associative translation lookaside buffer (TLB) including a least recently used (LRU) stack and implementing an LRU replacement strategy'
[patent_app_type] => B1
[patent_app_number] => 09/415132
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[pdf_file] => patents/06/453/06453387.pdf
[firstpage_image] =>[orig_patent_app_number] => 09415132
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/415132 | Fully associative translation lookaside buffer (TLB) including a least recently used (LRU) stack and implementing an LRU replacement strategy | Oct 7, 1999 | Issued |
Array
(
[id] => 1443906
[patent_doc_number] => 06336167
[patent_country] => US
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[patent_issue_date] => 2002-01-01
[patent_title] => 'Cache storage management using dual stacks'
[patent_app_type] => B1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/415416 | Cache storage management using dual stacks | Oct 7, 1999 | Issued |
Array
(
[id] => 1416780
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[patent_title] => 'Asochronous centralized multi-channel DMA controller'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/409820 | Asochronous centralized multi-channel DMA controller | Sep 29, 1999 | Issued |
Array
(
[id] => 1432391
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[patent_title] => 'Efficient memory allocator utilizing a dual free-list structure'
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Array
(
[id] => 1365257
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[patent_title] => 'Data storage system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/408058 | Data storage system | Sep 28, 1999 | Issued |
Array
(
[id] => 1466234
[patent_doc_number] => 06393534
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[patent_issue_date] => 2002-05-21
[patent_title] => 'Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory'
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Array
(
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[patent_title] => 'Architecture for multi-queue storage element'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/406042 | Architecture for multi-queue storage element | Sep 26, 1999 | Issued |
Array
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[patent_title] => 'Circuit and method for detecting bank conflicts in accessing adjacent banks'
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Array
(
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