Search

Abu Z. Ghaffari

Examiner (ID: 4367, Phone: (571)270-3799 , Office: P/2195 )

Most Active Art Unit
2195
Art Unit(s)
2195
Total Applications
723
Issued Applications
520
Pending Applications
72
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1431429 [patent_doc_number] => 06519684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Low overhead method for selecting and updating an entry in a cache memory' [patent_app_type] => B1 [patent_app_number] => 09/447254 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519684.pdf [firstpage_image] =>[orig_patent_app_number] => 09447254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447254
Low overhead method for selecting and updating an entry in a cache memory Nov 22, 1999 Issued
Array ( [id] => 1311345 [patent_doc_number] => 06625708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method and apparatus for dynamically defining line buffer configurations' [patent_app_type] => B1 [patent_app_number] => 09/447536 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3337 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625708.pdf [firstpage_image] =>[orig_patent_app_number] => 09447536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447536
Method and apparatus for dynamically defining line buffer configurations Nov 22, 1999 Issued
Array ( [id] => 1329105 [patent_doc_number] => 06606687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Optimized hardware cleaning function for VIVT data cache' [patent_app_type] => B1 [patent_app_number] => 09/447194 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4555 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606687.pdf [firstpage_image] =>[orig_patent_app_number] => 09447194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447194
Optimized hardware cleaning function for VIVT data cache Nov 21, 1999 Issued
Array ( [id] => 1206886 [patent_doc_number] => 06721859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Multi-protocol media storage device implementing protocols optimized for storing and retrieving both asynchronous and isochronous data' [patent_app_type] => B1 [patent_app_number] => 09/422870 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8023 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721859.pdf [firstpage_image] =>[orig_patent_app_number] => 09422870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422870
Multi-protocol media storage device implementing protocols optimized for storing and retrieving both asynchronous and isochronous data Oct 20, 1999 Issued
Array ( [id] => 1429289 [patent_doc_number] => 06530001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Computer system controlling memory clock signal and method for controlling the same' [patent_app_type] => B1 [patent_app_number] => 09/419774 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 5772 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530001.pdf [firstpage_image] =>[orig_patent_app_number] => 09419774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419774
Computer system controlling memory clock signal and method for controlling the same Oct 17, 1999 Issued
Array ( [id] => 4391526 [patent_doc_number] => 06289413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Cached synchronous DRAM architecture having a mode register programmable cache policy' [patent_app_type] => 1 [patent_app_number] => 9/360373 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7614 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289413.pdf [firstpage_image] =>[orig_patent_app_number] => 360373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360373
Cached synchronous DRAM architecture having a mode register programmable cache policy Oct 14, 1999 Issued
Array ( [id] => 1584619 [patent_doc_number] => 06449665 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Means for reducing direct memory access' [patent_app_type] => B1 [patent_app_number] => 09/419690 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3684 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449665.pdf [firstpage_image] =>[orig_patent_app_number] => 09419690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419690
Means for reducing direct memory access Oct 13, 1999 Issued
Array ( [id] => 1236319 [patent_doc_number] => 06694422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Semiconductor memory device having adjustable page length and page depth' [patent_app_type] => B1 [patent_app_number] => 09/419711 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4327 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694422.pdf [firstpage_image] =>[orig_patent_app_number] => 09419711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419711
Semiconductor memory device having adjustable page length and page depth Oct 13, 1999 Issued
09/418184 SYSTEM AND METHOD FOR ASSIGNING RATINGS TO MUTUAL FUNDS AND OTHER INVESTMENT FUNDS BASED ON THE VALUE OF VARIOUS FUTURE AND OPTION SECURITIES Oct 11, 1999 Abandoned
Array ( [id] => 1557258 [patent_doc_number] => 06349365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'User-prioritized cache replacement' [patent_app_type] => B1 [patent_app_number] => 09/415892 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10958 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349365.pdf [firstpage_image] =>[orig_patent_app_number] => 09415892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415892
User-prioritized cache replacement Oct 7, 1999 Issued
Array ( [id] => 1567456 [patent_doc_number] => 06363464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Redundant processor controlled system' [patent_app_type] => B1 [patent_app_number] => 09/414915 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2104 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363464.pdf [firstpage_image] =>[orig_patent_app_number] => 09414915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414915
Redundant processor controlled system Oct 7, 1999 Issued
Array ( [id] => 1484966 [patent_doc_number] => 06453387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Fully associative translation lookaside buffer (TLB) including a least recently used (LRU) stack and implementing an LRU replacement strategy' [patent_app_type] => B1 [patent_app_number] => 09/415132 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17296 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453387.pdf [firstpage_image] =>[orig_patent_app_number] => 09415132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415132
Fully associative translation lookaside buffer (TLB) including a least recently used (LRU) stack and implementing an LRU replacement strategy Oct 7, 1999 Issued
Array ( [id] => 1443906 [patent_doc_number] => 06336167 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Cache storage management using dual stacks' [patent_app_type] => B1 [patent_app_number] => 09/415416 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2724 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336167.pdf [firstpage_image] =>[orig_patent_app_number] => 09415416 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415416
Cache storage management using dual stacks Oct 7, 1999 Issued
Array ( [id] => 1416780 [patent_doc_number] => 06532511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Asochronous centralized multi-channel DMA controller' [patent_app_type] => B1 [patent_app_number] => 09/409820 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3971 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532511.pdf [firstpage_image] =>[orig_patent_app_number] => 09409820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409820
Asochronous centralized multi-channel DMA controller Sep 29, 1999 Issued
Array ( [id] => 1432391 [patent_doc_number] => 06505283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Efficient memory allocator utilizing a dual free-list structure' [patent_app_type] => B1 [patent_app_number] => 09/409055 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5208 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505283.pdf [firstpage_image] =>[orig_patent_app_number] => 09409055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409055
Efficient memory allocator utilizing a dual free-list structure Sep 29, 1999 Issued
Array ( [id] => 1365257 [patent_doc_number] => 06581137 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Data storage system' [patent_app_type] => B1 [patent_app_number] => 09/408058 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8243 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581137.pdf [firstpage_image] =>[orig_patent_app_number] => 09408058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408058
Data storage system Sep 28, 1999 Issued
Array ( [id] => 1466234 [patent_doc_number] => 06393534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory' [patent_app_type] => B1 [patent_app_number] => 09/407131 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 13889 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393534.pdf [firstpage_image] =>[orig_patent_app_number] => 09407131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407131
Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory Sep 26, 1999 Issued
Array ( [id] => 1294807 [patent_doc_number] => 06640267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Architecture for multi-queue storage element' [patent_app_type] => B1 [patent_app_number] => 09/406042 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/640/06640267.pdf [firstpage_image] =>[orig_patent_app_number] => 09406042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406042
Architecture for multi-queue storage element Sep 26, 1999 Issued
Array ( [id] => 1466144 [patent_doc_number] => 06393512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Circuit and method for detecting bank conflicts in accessing adjacent banks' [patent_app_type] => B1 [patent_app_number] => 09/407224 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 13231 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393512.pdf [firstpage_image] =>[orig_patent_app_number] => 09407224 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407224
Circuit and method for detecting bank conflicts in accessing adjacent banks Sep 26, 1999 Issued
Array ( [id] => 1481754 [patent_doc_number] => 06345347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Address protection using a hardware-defined application key' [patent_app_type] => B1 [patent_app_number] => 09/406527 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3801 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345347.pdf [firstpage_image] =>[orig_patent_app_number] => 09406527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406527
Address protection using a hardware-defined application key Sep 26, 1999 Issued
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