Abu Z. Ghaffari

Array ( [id] => 1438675 [patent_doc_number] => 06356982 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Dynamic mechanism to upgrade o state memory-consistent cache lines' [patent_app_type] => B1 [patent_app_number] => 09/339405 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7225 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356982.pdf [firstpage_image] =>[orig_patent_app_number] => 09339405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1474905 [patent_doc_number] => 06408362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data' [patent_app_type] => B1 [patent_app_number] => 09/339402 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3295 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408362.pdf [firstpage_image] =>[orig_patent_app_number] => 09339402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1557268 [patent_doc_number] => 06349368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'High performance mechanism to support O state horizontal cache-to-cache transfers' [patent_app_type] => B1 [patent_app_number] => 09/339406 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6999 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349368.pdf [firstpage_image] =>[orig_patent_app_number] => 09339406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7638618 [patent_doc_number] => 06397303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines' [patent_app_type] => B1 [patent_app_number] => 09/339408 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7200 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397303.pdf [firstpage_image] =>[orig_patent_app_number] => 09339408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1604492 [patent_doc_number] => 06434678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method for data storage organization' [patent_app_type] => B1 [patent_app_number] => 09/337305 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2321 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434678.pdf [firstpage_image] =>[orig_patent_app_number] => 09337305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423366 [patent_doc_number] => 06311253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Methods for caching cache tags' [patent_app_type] => 1 [patent_app_number] => 9/336953 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6134 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311253.pdf [firstpage_image] =>[orig_patent_app_number] => 336953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431904 [patent_doc_number] => 06516400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Data storage, data processing system and method' [patent_app_type] => B1 [patent_app_number] => 09/334667 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5824 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516400.pdf [firstpage_image] =>[orig_patent_app_number] => 09334667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4294793 [patent_doc_number] => 06324631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method and system for detecting and coalescing free areas during garbage collection' [patent_app_type] => 1 [patent_app_number] => 9/335285 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5010 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324631.pdf [firstpage_image] =>[orig_patent_app_number] => 335285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466177 [patent_doc_number] => 06393519 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Disk array controller with connection path formed on connection request queue basis' [patent_app_type] => B1 [patent_app_number] => 09/334599 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5790 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393519.pdf [firstpage_image] =>[orig_patent_app_number] => 09334599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1501519 [patent_doc_number] => 06405279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Apparatus and method for controlling rewriting of data into nonvolatile memory' [patent_app_type] => B1 [patent_app_number] => 09/329238 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3452 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405279.pdf [firstpage_image] =>[orig_patent_app_number] => 09329238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1604469 [patent_doc_number] => 06434655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Fast access to buffer circuits' [patent_app_type] => B1 [patent_app_number] => 09/324338 [patent_app_country] => US [patent_app_date] => 1999-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3555 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434655.pdf [firstpage_image] =>[orig_patent_app_number] => 09324338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1533153 [patent_doc_number] => 06480942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Synchronized FIFO memory circuit' [patent_app_type] => B1 [patent_app_number] => 09/320720 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7184 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480942.pdf [firstpage_image] =>[orig_patent_app_number] => 09320720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1604454 [patent_doc_number] => 06434640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Unload counter adjust logic for a receiver buffer' [patent_app_type] => B1 [patent_app_number] => 09/320134 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6585 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434640.pdf [firstpage_image] =>[orig_patent_app_number] => 09320134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644142 [patent_doc_number] => 06473832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Load/store unit having pre-cache and post-cache queues for low latency load memory operations' [patent_app_type] => B1 [patent_app_number] => 09/314035 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 27587 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473832.pdf [firstpage_image] =>[orig_patent_app_number] => 09314035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644137 [patent_doc_number] => 06473837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Snoop resynchronization mechanism to preserve read ordering' [patent_app_type] => B1 [patent_app_number] => 09/314036 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 28338 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473837.pdf [firstpage_image] =>[orig_patent_app_number] => 09314036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429224 [patent_doc_number] => 06529994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method of striping data onto a storage array' [patent_app_type] => B1 [patent_app_number] => 09/313408 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10818 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529994.pdf [firstpage_image] =>[orig_patent_app_number] => 09313408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587284 [patent_doc_number] => 06425024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Buffer management for improved PCI-X or PCI bridge performance' [patent_app_type] => B1 [patent_app_number] => 09/314044 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3781 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425024.pdf [firstpage_image] =>[orig_patent_app_number] => 09314044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462425 [patent_doc_number] => 06427193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Deadlock avoidance using exponential backoff' [patent_app_type] => B1 [patent_app_number] => 09/313670 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 28056 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427193.pdf [firstpage_image] =>[orig_patent_app_number] => 09313670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587448 [patent_doc_number] => 06425066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Integrated circuit comprising at least two memories' [patent_app_type] => B1 [patent_app_number] => 09/313926 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4620 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425066.pdf [firstpage_image] =>[orig_patent_app_number] => 09313926 [rel_patent_id] =>[rel_patent_doc_number] =>)