Search

Abul Kalam

Examiner (ID: 1931, Phone: (571)272-8346 , Office: P/2896 )

Most Active Art Unit
2896
Art Unit(s)
2896, 2829, 2814
Total Applications
749
Issued Applications
470
Pending Applications
11
Abandoned Applications
275

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16495897 [patent_doc_number] => 10861949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Thin film transistor substrate [patent_app_type] => utility [patent_app_number] => 16/192802 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4970 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192802
Thin film transistor substrate Nov 15, 2018 Issued
Array ( [id] => 13936539 [patent_doc_number] => 20190051785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => ACTIVE PHOTONIC DEVICE HAVING A DARLINGTON CONFIGURATION WITH FEEDBACK [patent_app_type] => utility [patent_app_number] => 16/167788 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167788 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/167788
Active photonic device having a darlington configuration with feedback Oct 22, 2018 Issued
Array ( [id] => 16609415 [patent_doc_number] => 10910431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Pixel with strained silicon layer for improving carrier mobility and blue response in imagers [patent_app_type] => utility [patent_app_number] => 16/161653 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4701 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16161653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/161653
Pixel with strained silicon layer for improving carrier mobility and blue response in imagers Oct 15, 2018 Issued
Array ( [id] => 17366124 [patent_doc_number] => 11233157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Systems and methods for unipolar charge balanced semiconductor power devices [patent_app_type] => utility [patent_app_number] => 16/147210 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9873 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147210
Systems and methods for unipolar charge balanced semiconductor power devices Sep 27, 2018 Issued
Array ( [id] => 15718029 [patent_doc_number] => 20200105782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => VERTICAL CHANNEL STRUCTURE AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/147065 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147065 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147065
VERTICAL CHANNEL STRUCTURE AND MEMORY DEVICE Sep 27, 2018 Abandoned
Array ( [id] => 15718315 [patent_doc_number] => 20200105925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => TECHNIQUES FOR FABRICATING CHARGE BALANCED (CB) TRENCH-METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) DEVICES [patent_app_type] => utility [patent_app_number] => 16/147216 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147216
Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices Sep 27, 2018 Issued
Array ( [id] => 13909713 [patent_doc_number] => 20190044061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MEMORY CELLS HAVING INCREASED STRUCTURAL STABILITY [patent_app_type] => utility [patent_app_number] => 16/147159 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147159 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147159
Memory cells having increased structural stability Sep 27, 2018 Issued
Array ( [id] => 15154717 [patent_doc_number] => 20190355836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => MANUFACTURING METHOD FOR AMORPHOUS SILICON TFT SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/313045 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 729 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16313045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/313045
MANUFACTURING METHOD FOR AMORPHOUS SILICON TFT SUBSTRATE Sep 26, 2018 Abandoned
Array ( [id] => 17270417 [patent_doc_number] => 11195846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Staircase structures for three-dimensional memory device double-sided routing [patent_app_type] => utility [patent_app_number] => 16/139000 [patent_app_country] => US [patent_app_date] => 2018-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139000 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139000
Staircase structures for three-dimensional memory device double-sided routing Sep 21, 2018 Issued
Array ( [id] => 16464173 [patent_doc_number] => 10847534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Staircase structures for three-dimensional memory device double-sided routing [patent_app_type] => utility [patent_app_number] => 16/138994 [patent_app_country] => US [patent_app_date] => 2018-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138994 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138994
Staircase structures for three-dimensional memory device double-sided routing Sep 21, 2018 Issued
Array ( [id] => 13785679 [patent_doc_number] => 20190006378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => NONVOLATILE MEMORY STRUCTURE AND ARRAY [patent_app_type] => utility [patent_app_number] => 16/122898 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122898 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/122898
Nonvolatile memory structure and array Sep 5, 2018 Issued
Array ( [id] => 14317527 [patent_doc_number] => 20190148467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/124067 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124067
Display device Sep 5, 2018 Issued
Array ( [id] => 13613265 [patent_doc_number] => 20180358182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => METHOD FOR PRODUCING A LAYER WITH PEROVSKITE MATERIAL [patent_app_type] => utility [patent_app_number] => 16/104732 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104732 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/104732
METHOD FOR PRODUCING A LAYER WITH PEROVSKITE MATERIAL Aug 16, 2018 Abandoned
Array ( [id] => 13963063 [patent_doc_number] => 20190057876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/057255 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057255 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057255
Semiconductor device and fabrication method thereof Aug 6, 2018 Issued
Array ( [id] => 16957576 [patent_doc_number] => 11061435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/055006 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5037 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/055006
Display device Aug 2, 2018 Issued
Array ( [id] => 13598215 [patent_doc_number] => 20180350656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/049938 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049938 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049938
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Jul 30, 2018 Abandoned
Array ( [id] => 13598287 [patent_doc_number] => 20180350692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Semiconductor Structure and Manufacturing Method Thereof [patent_app_type] => utility [patent_app_number] => 16/050028 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050028 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050028
Semiconductor structure and manufacturing method thereof Jul 30, 2018 Issued
Array ( [id] => 13598599 [patent_doc_number] => 20180350848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/047875 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047875
Thin film transistor substrate and method for manufacturing the same Jul 26, 2018 Issued
Array ( [id] => 13598505 [patent_doc_number] => 20180350801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => Recessed STI as the Gate Dielectric of HV Device [patent_app_type] => utility [patent_app_number] => 16/045252 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/045252
Recessed STI as the gate dielectric of HV device Jul 24, 2018 Issued
Array ( [id] => 17181545 [patent_doc_number] => 11158797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => RRAM cell structure with conductive etch-stop layer [patent_app_type] => utility [patent_app_number] => 16/009327 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16009327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/009327
RRAM cell structure with conductive etch-stop layer Jun 14, 2018 Issued
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