Adam D. Houston

Array ( [id] => 19460577 [patent_doc_number] => 12101095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Fractional divider with duty cycle regulation and low subharmonic content [patent_app_type] => utility [patent_app_number] => 18/317582 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500995 [patent_doc_number] => 20240340013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => DELAY LOCKED LOOP [patent_app_type] => utility [patent_app_number] => 18/311251 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19559825 [patent_doc_number] => 20240371617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => PLASMA GENERATION QUALITY MONITORING USING MULTI-CHANNEL SENSOR DATA [patent_app_type] => utility [patent_app_number] => 18/142546 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20360633 [patent_doc_number] => 12476641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Clock selection method for multiplying delay locked loop [patent_app_type] => utility [patent_app_number] => 18/136017 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 1029 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18136017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19357381 [patent_doc_number] => 12057846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Delay lock loop circuits and methods for operating same [patent_app_type] => utility [patent_app_number] => 18/301299 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18899372 [patent_doc_number] => 20240014857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Wireless Power Transfer With In-Band Virtualized Wired Communications [patent_app_type] => utility [patent_app_number] => 18/298072 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18899372 [patent_doc_number] => 20240014857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Wireless Power Transfer With In-Band Virtualized Wired Communications [patent_app_type] => utility [patent_app_number] => 18/298072 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18899372 [patent_doc_number] => 20240014857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Wireless Power Transfer With In-Band Virtualized Wired Communications [patent_app_type] => utility [patent_app_number] => 18/298072 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18899372 [patent_doc_number] => 20240014857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Wireless Power Transfer With In-Band Virtualized Wired Communications [patent_app_type] => utility [patent_app_number] => 18/298072 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18797477 [patent_doc_number] => 11831322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Digitally calibrated programmable clock phase generation circuit [patent_app_type] => utility [patent_app_number] => 18/126889 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19261466 [patent_doc_number] => 12021539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-25 [patent_title] => Phase locked loop frequency synthesizer with translation reference loop [patent_app_type] => utility [patent_app_number] => 18/126380 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8310 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18975992 [patent_doc_number] => 20240056084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 18/189599 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18834491 [patent_doc_number] => 20230403018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT, PHASE LOCKED LOOP (PLL) CIRCUIT, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/176339 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18790176 [patent_doc_number] => 20230378961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => METHODS AND APPARATUS TO RETIME DATA USING A PROGRAMMABLE DELAY [patent_app_type] => utility [patent_app_number] => 18/115682 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18115682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18730135 [patent_doc_number] => 20230344433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => PERIOD ERROR CORRECTION IN DIGITAL FREQUENCY LOCKED LOOPS [patent_app_type] => utility [patent_app_number] => 18/114595 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18697217 [patent_doc_number] => 20230327676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => ULTRA-LOW POWER INSTANT LOCK PHASE LOCK LOOP (PLL) [patent_app_type] => utility [patent_app_number] => 18/113601 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19109190 [patent_doc_number] => 11962309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Phase adjusting circuit, delay locking circuit, and memory [patent_app_type] => utility [patent_app_number] => 18/169285 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9204 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19180570 [patent_doc_number] => 11987148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-21 [patent_title] => Optimal control strategy for a distributed low voltage system with unidirectional direct current converters [patent_app_type] => utility [patent_app_number] => 18/168750 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18849769 [patent_doc_number] => 20230412173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => DELAY LOCKED LOOP CIRCUITRY AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/166169 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19109193 [patent_doc_number] => 11962312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Frequency-locked and phase-locked loop-based clock glitch detection for security [patent_app_type] => utility [patent_app_number] => 18/106398 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8683 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106398 [rel_patent_id] =>[rel_patent_doc_number] =>)