
Adam S. Bowen
Examiner (ID: 19031, Phone: (571)272-3984 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897 |
| Total Applications | 851 |
| Issued Applications | 777 |
| Pending Applications | 68 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18533249
[patent_doc_number] => 20230238325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-27
[patent_title] => TRENCH POWER RAIL IN CELL CIRCUITS TO REDUCE RESISTANCE AND RELATED POWER DISTRIBUTION NETWORKS AND FABRICATION METHODS
[patent_app_type] => utility
[patent_app_number] => 17/648981
[patent_app_country] => US
[patent_app_date] => 2022-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11979
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648981
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648981 | Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods | Jan 25, 2022 | Issued |
Array
(
[id] => 19153855
[patent_doc_number] => 11978779
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-07
[patent_title] => Semiconductor device and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/580847
[patent_app_country] => US
[patent_app_date] => 2022-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 54
[patent_no_of_words] => 15106
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580847
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/580847 | Semiconductor device and method of fabricating the same | Jan 20, 2022 | Issued |
Array
(
[id] => 18983676
[patent_doc_number] => 11908865
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Semiconductor structure and fabrication method thereof
[patent_app_type] => utility
[patent_app_number] => 17/576876
[patent_app_country] => US
[patent_app_date] => 2022-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 8951
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576876
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/576876 | Semiconductor structure and fabrication method thereof | Jan 13, 2022 | Issued |
Array
(
[id] => 20405704
[patent_doc_number] => 12495695
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-09
[patent_title] => OLED display panel and laser repair method thereof
[patent_app_type] => utility
[patent_app_number] => 17/922385
[patent_app_country] => US
[patent_app_date] => 2022-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2556
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17922385
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/922385 | OLED display panel and laser repair method thereof | Jan 6, 2022 | Issued |
Array
(
[id] => 18704917
[patent_doc_number] => 11791436
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-17
[patent_title] => Semiconductor light emitting device and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/570206
[patent_app_country] => US
[patent_app_date] => 2022-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 46
[patent_no_of_words] => 9567
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570206
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/570206 | Semiconductor light emitting device and method of fabricating the same | Jan 5, 2022 | Issued |
Array
(
[id] => 18473180
[patent_doc_number] => 20230207468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => STACKED STAIRCASE CMOS WITH BURIED POWER RAIL
[patent_app_type] => utility
[patent_app_number] => 17/563653
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5902
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563653
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/563653 | STACKED STAIRCASE CMOS WITH BURIED POWER RAIL | Dec 27, 2021 | Abandoned |
Array
(
[id] => 18580735
[patent_doc_number] => 11737284
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-22
[patent_title] => Tunnel junction selector MRAM
[patent_app_type] => utility
[patent_app_number] => 17/562680
[patent_app_country] => US
[patent_app_date] => 2021-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 37
[patent_no_of_words] => 9822
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562680
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/562680 | Tunnel junction selector MRAM | Dec 26, 2021 | Issued |
Array
(
[id] => 18579010
[patent_doc_number] => 11735550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-22
[patent_title] => Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion
[patent_app_type] => utility
[patent_app_number] => 17/555854
[patent_app_country] => US
[patent_app_date] => 2021-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 8247
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555854
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/555854 | Bump structure to prevent metal redeposit and to prevent bond pad consumption and corrosion | Dec 19, 2021 | Issued |
Array
(
[id] => 17523053
[patent_doc_number] => 20220108902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-07
[patent_title] => AUTO-CALIBRATION TO A STATION OF A PROCESS MODULE THAT SPINS A WAFER
[patent_app_type] => utility
[patent_app_number] => 17/553658
[patent_app_country] => US
[patent_app_date] => 2021-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13907
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553658
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/553658 | Auto-calibration to a station of a process module that spins a wafer | Dec 15, 2021 | Issued |
Array
(
[id] => 18464343
[patent_doc_number] => 11688637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-27
[patent_title] => Wrap-around contact structures for semiconductor fins
[patent_app_type] => utility
[patent_app_number] => 17/542191
[patent_app_country] => US
[patent_app_date] => 2021-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 41
[patent_no_of_words] => 16764
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542191
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/542191 | Wrap-around contact structures for semiconductor fins | Dec 2, 2021 | Issued |
Array
(
[id] => 18433247
[patent_doc_number] => 11678489
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Three-dimensional flash memory device including channel structures having enlarged portions
[patent_app_type] => utility
[patent_app_number] => 17/532271
[patent_app_country] => US
[patent_app_date] => 2021-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 10473
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532271
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/532271 | Three-dimensional flash memory device including channel structures having enlarged portions | Nov 21, 2021 | Issued |
Array
(
[id] => 18307103
[patent_doc_number] => 20230111003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-13
[patent_title] => FIELD EFFECT TRANSISTORS WITH REDUCED GATE FRINGE AREA AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/529802
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 28513
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529802
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529802 | Field effect transistors with reduced gate fringe area and method of making the same | Nov 17, 2021 | Issued |
Array
(
[id] => 18464495
[patent_doc_number] => 11688792
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-27
[patent_title] => Dual self-aligned gate endcap (SAGE) architectures
[patent_app_type] => utility
[patent_app_number] => 17/526986
[patent_app_country] => US
[patent_app_date] => 2021-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 26
[patent_no_of_words] => 13917
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526986
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/526986 | Dual self-aligned gate endcap (SAGE) architectures | Nov 14, 2021 | Issued |
Array
(
[id] => 19611022
[patent_doc_number] => 12159904
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-03
[patent_title] => Cell placement optimization
[patent_app_type] => utility
[patent_app_number] => 17/523033
[patent_app_country] => US
[patent_app_date] => 2021-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6809
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523033
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/523033 | Cell placement optimization | Nov 9, 2021 | Issued |
Array
(
[id] => 18197642
[patent_doc_number] => 20230051161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => FinFET STANDARD CELL WITH DOUBLE SELF-ALIGNED CONTACTS AND METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 17/522781
[patent_app_country] => US
[patent_app_date] => 2021-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4184
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522781
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/522781 | FinFET standard cell with double self-aligned contacts and method therefor | Nov 8, 2021 | Issued |
Array
(
[id] => 18236057
[patent_doc_number] => 11600624
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Semiconductor structure with dielectric fin in memory cell and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/521389
[patent_app_country] => US
[patent_app_date] => 2021-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 10210
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521389
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/521389 | Semiconductor structure with dielectric fin in memory cell and method for forming the same | Nov 7, 2021 | Issued |
Array
(
[id] => 19341502
[patent_doc_number] => 12051699
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Semiconductor structure and method for forming same
[patent_app_type] => utility
[patent_app_number] => 17/520794
[patent_app_country] => US
[patent_app_date] => 2021-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 10252
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520794
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/520794 | Semiconductor structure and method for forming same | Nov 7, 2021 | Issued |
Array
(
[id] => 17431767
[patent_doc_number] => 20220059476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITANCE TO SURFACE MOUNTED DIE
[patent_app_type] => utility
[patent_app_number] => 17/518504
[patent_app_country] => US
[patent_app_date] => 2021-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6931
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518504
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/518504 | Capacitor die embedded in package substrate for providing capacitance to surface mounted die | Nov 2, 2021 | Issued |
Array
(
[id] => 18351288
[patent_doc_number] => 20230139399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-04
[patent_title] => STRESSED MATERIAL WITHIN GATE CUT REGION
[patent_app_type] => utility
[patent_app_number] => 17/516505
[patent_app_country] => US
[patent_app_date] => 2021-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15055
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516505
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/516505 | Stressed material within gate cut region | Oct 31, 2021 | Issued |
Array
(
[id] => 17402910
[patent_doc_number] => 20220045001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET) AS ANTIFUSE ELEMENTS
[patent_app_type] => utility
[patent_app_number] => 17/510190
[patent_app_country] => US
[patent_app_date] => 2021-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10793
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510190
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/510190 | Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements | Oct 24, 2021 | Issued |