Search

Adam S. Bowen

Examiner (ID: 19031, Phone: (571)272-3984 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897
Total Applications
851
Issued Applications
777
Pending Applications
68
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19484366 [patent_doc_number] => 20240332408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => Isolation Structures [patent_app_type] => utility [patent_app_number] => 18/194477 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194477
Isolation Structures Mar 30, 2023 Pending
Array ( [id] => 19071299 [patent_doc_number] => 20240105725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => CFET WITH ASYMMETRIC SOURCE/DRAIN FEATURES [patent_app_type] => utility [patent_app_number] => 18/193087 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193087 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193087
CFET with asymmetric source/drain features Mar 29, 2023 Issued
Array ( [id] => 19054990 [patent_doc_number] => 20240096959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => Profile Control of Epitaxial Structures in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/128051 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18128051 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/128051
Profile control of epitaxial structures in semiconductor devices Mar 28, 2023 Issued
Array ( [id] => 19468295 [patent_doc_number] => 20240321965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SELECTIVE CONTACT ON SOURCE AND DRAIN [patent_app_type] => utility [patent_app_number] => 18/189442 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189442
Selective contact on source and drain Mar 23, 2023 Issued
Array ( [id] => 19146220 [patent_doc_number] => 20240145249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR DEVICE WITH GATE ISOLATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/189708 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189708
Semiconductor device with gate isolation structure Mar 23, 2023 Issued
Array ( [id] => 19285887 [patent_doc_number] => 20240222364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING [patent_app_type] => utility [patent_app_number] => 18/188937 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18188937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/188937
INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING Mar 22, 2023 Pending
Array ( [id] => 19468343 [patent_doc_number] => 20240322013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/188964 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18188964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/188964
Semiconductor structure and method for manufacturing the same Mar 22, 2023 Issued
Array ( [id] => 19370626 [patent_doc_number] => 12062720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Epitaxial source/drain structure and method of forming same [patent_app_type] => utility [patent_app_number] => 18/186244 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 9538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/186244
Epitaxial source/drain structure and method of forming same Mar 19, 2023 Issued
Array ( [id] => 19243031 [patent_doc_number] => 12013463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Light-sensing apparatus and light-sensing method thereof [patent_app_type] => utility [patent_app_number] => 18/121295 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 158 [patent_no_of_words] => 53760 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121295
Light-sensing apparatus and light-sensing method thereof Mar 13, 2023 Issued
Array ( [id] => 20531859 [patent_doc_number] => 12550310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Gate isolation structures [patent_app_type] => utility [patent_app_number] => 18/180968 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180968
Gate isolation structures Mar 8, 2023 Issued
Array ( [id] => 19399685 [patent_doc_number] => 12074071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Source/drain structures and method of forming [patent_app_type] => utility [patent_app_number] => 18/178640 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 77 [patent_no_of_words] => 11544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178640
Source/drain structures and method of forming Mar 5, 2023 Issued
Array ( [id] => 19330436 [patent_doc_number] => 12048136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Semiconductor structure with dielectric fin in memory cell and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/178723 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178723 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178723
Semiconductor structure with dielectric fin in memory cell and method for forming the same Mar 5, 2023 Issued
Array ( [id] => 18473401 [patent_doc_number] => 20230207689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/174952 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174952
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Feb 26, 2023 Abandoned
Array ( [id] => 18456576 [patent_doc_number] => 20230197858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/110961 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110961
Semiconductor device Feb 16, 2023 Issued
Array ( [id] => 19598600 [patent_doc_number] => 12156478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/110337 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3526 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110337 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110337
Semiconductor device and method for fabricating the same Feb 14, 2023 Issued
Array ( [id] => 19277464 [patent_doc_number] => 12027597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Semiconductor device structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/108890 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108890 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/108890
Semiconductor device structure and methods of forming the same Feb 12, 2023 Issued
Array ( [id] => 19277240 [patent_doc_number] => 12027372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Contact structures with deposited silicide layers [patent_app_type] => utility [patent_app_number] => 18/097323 [patent_app_country] => US [patent_app_date] => 2023-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097323
Contact structures with deposited silicide layers Jan 15, 2023 Issued
Array ( [id] => 20540248 [patent_doc_number] => 12557335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Transistor structure [patent_app_type] => utility [patent_app_number] => 18/093420 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 42 [patent_no_of_words] => 2176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093420 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093420
Transistor structure Jan 4, 2023 Issued
Array ( [id] => 19285793 [patent_doc_number] => 20240222270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => VIA FUSE WITH METAL-INSULATOR-METAL ARCHITECTURE AND IMPROVED ELECTRODE MATERIAL [patent_app_type] => utility [patent_app_number] => 18/148147 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148147
VIA FUSE WITH METAL-INSULATOR-METAL ARCHITECTURE AND IMPROVED ELECTRODE MATERIAL Dec 28, 2022 Pending
Array ( [id] => 19328910 [patent_doc_number] => 12046600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Techniques for achieving multiple transistor fin dimensions on a single die [patent_app_type] => utility [patent_app_number] => 18/088463 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088463
Techniques for achieving multiple transistor fin dimensions on a single die Dec 22, 2022 Issued
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