
Adam S. Bowen
Examiner (ID: 19031, Phone: (571)272-3984 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897 |
| Total Applications | 851 |
| Issued Applications | 777 |
| Pending Applications | 68 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19269544
[patent_doc_number] => 20240213248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => STACKED TRANSISTORS HAVING SELF ALIGNED BACKSIDE CONTACT WITH BACKSIDE REPLACEMENT METAL GATE
[patent_app_type] => utility
[patent_app_number] => 18/145034
[patent_app_country] => US
[patent_app_date] => 2022-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13259
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145034
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/145034 | Stacked transistors having self aligned backside contact with backside replacement metal gate | Dec 21, 2022 | Issued |
Array
(
[id] => 19269412
[patent_doc_number] => 20240213116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO COOL INTEGRATED CIRCUIT PACKAGES HAVING GLASS SUBSTRATES
[patent_app_type] => utility
[patent_app_number] => 18/069507
[patent_app_country] => US
[patent_app_date] => 2022-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14677
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069507
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/069507 | METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO COOL INTEGRATED CIRCUIT PACKAGES HAVING GLASS SUBSTRATES | Dec 20, 2022 | Pending |
Array
(
[id] => 19401196
[patent_doc_number] => 12075607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-27
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/069765
[patent_app_country] => US
[patent_app_date] => 2022-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5548
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069765
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/069765 | Semiconductor device | Dec 20, 2022 | Issued |
Array
(
[id] => 18321685
[patent_doc_number] => 20230119813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => SOURCE/DRAIN EPI STRUCTURE FOR IMPROVING CONTACT QUALITY
[patent_app_type] => utility
[patent_app_number] => 18/068687
[patent_app_country] => US
[patent_app_date] => 2022-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12316
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068687
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/068687 | Source/drain EPI structure for improving contact quality | Dec 19, 2022 | Issued |
Array
(
[id] => 18334283
[patent_doc_number] => 20230126231
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => METHOD AND APPARATUS FOR FILLING A RECESS FORMED WITHIN A SUBSTRATE SURFACE
[patent_app_type] => utility
[patent_app_number] => 18/084789
[patent_app_country] => US
[patent_app_date] => 2022-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5173
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084789
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/084789 | Method and apparatus for filling a recess formed within a substrate surface | Dec 19, 2022 | Issued |
Array
(
[id] => 18324853
[patent_doc_number] => 20230122981
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => Gapfill Structure and Manufacturing Methods Thereof
[patent_app_type] => utility
[patent_app_number] => 18/083757
[patent_app_country] => US
[patent_app_date] => 2022-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10049
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083757
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/083757 | Gapfill structure and manufacturing methods thereof | Dec 18, 2022 | Issued |
Array
(
[id] => 18325542
[patent_doc_number] => 20230123670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 18/068257
[patent_app_country] => US
[patent_app_date] => 2022-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19920
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068257
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/068257 | Semiconductor devices and methods of manufacture | Dec 18, 2022 | Issued |
Array
(
[id] => 18325740
[patent_doc_number] => 20230123868
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => Semiconductor Device and Method
[patent_app_type] => utility
[patent_app_number] => 18/068075
[patent_app_country] => US
[patent_app_date] => 2022-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12110
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068075
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/068075 | Semiconductor device and method | Dec 18, 2022 | Issued |
Array
(
[id] => 19200580
[patent_doc_number] => 11997844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-28
[patent_title] => SRAM structures with improved write word line placement
[patent_app_type] => utility
[patent_app_number] => 18/067003
[patent_app_country] => US
[patent_app_date] => 2022-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 11594
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067003
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/067003 | SRAM structures with improved write word line placement | Dec 14, 2022 | Issued |
Array
(
[id] => 19237333
[patent_doc_number] => 20240194528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => BACKSIDE DIRECT CONTACT FORMATION
[patent_app_type] => utility
[patent_app_number] => 18/065060
[patent_app_country] => US
[patent_app_date] => 2022-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5638
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18065060
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/065060 | Backside direct contact formation | Dec 12, 2022 | Issued |
Array
(
[id] => 19213781
[patent_doc_number] => 12002855
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-04
[patent_title] => Method of manufacturing a semiconductor device and a semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/075172
[patent_app_country] => US
[patent_app_date] => 2022-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 30
[patent_no_of_words] => 9533
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075172
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/075172 | Method of manufacturing a semiconductor device and a semiconductor device | Dec 4, 2022 | Issued |
Array
(
[id] => 19168450
[patent_doc_number] => 11984363
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-14
[patent_title] => Dual silicide structure and methods thereof
[patent_app_type] => utility
[patent_app_number] => 18/070268
[patent_app_country] => US
[patent_app_date] => 2022-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10809
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070268
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/070268 | Dual silicide structure and methods thereof | Nov 27, 2022 | Issued |
Array
(
[id] => 18270135
[patent_doc_number] => 20230091377
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => Asymmetric Epitaxy Regions for Landing Contact Plug
[patent_app_type] => utility
[patent_app_number] => 17/994534
[patent_app_country] => US
[patent_app_date] => 2022-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8280
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994534
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/994534 | Asymmetric epitaxy regions for landing contact plug | Nov 27, 2022 | Issued |
Array
(
[id] => 19191456
[patent_doc_number] => 20240170369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => SELF-ALIGNED BACKSIDE GATE CONTACT
[patent_app_type] => utility
[patent_app_number] => 18/057888
[patent_app_country] => US
[patent_app_date] => 2022-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5631
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18057888
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/057888 | Self-aligned backside gate contact | Nov 21, 2022 | Issued |
Array
(
[id] => 18251661
[patent_doc_number] => 20230078700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => Gate-All-Around Device With Different Channel Semiconductor Materials And Method Of Forming The Same
[patent_app_type] => utility
[patent_app_number] => 17/991153
[patent_app_country] => US
[patent_app_date] => 2022-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12127
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991153
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/991153 | Gate-all-around device with different channel semiconductor materials and method of forming the same | Nov 20, 2022 | Issued |
Array
(
[id] => 18257781
[patent_doc_number] => 20230084821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => Semiconductor Devices and Methods of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 18/055498
[patent_app_country] => US
[patent_app_date] => 2022-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9440
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18055498
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/055498 | Semiconductor devices and methods of forming the same | Nov 14, 2022 | Issued |
Array
(
[id] => 20244162
[patent_doc_number] => 12424493
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-23
[patent_title] => Self-aligned double patterning with mandrel manipulation
[patent_app_type] => utility
[patent_app_number] => 17/985487
[patent_app_country] => US
[patent_app_date] => 2022-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985487
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/985487 | Self-aligned double patterning with mandrel manipulation | Nov 10, 2022 | Issued |
Array
(
[id] => 18456443
[patent_doc_number] => 20230197725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => INTEGRATED STRUCTURE OF COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/052950
[patent_app_country] => US
[patent_app_date] => 2022-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26942
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 977
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052950
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/052950 | INTEGRATED STRUCTURE OF COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF | Nov 6, 2022 | Abandoned |
Array
(
[id] => 20307227
[patent_doc_number] => 12453238
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Display apparatus
[patent_app_type] => utility
[patent_app_number] => 17/982314
[patent_app_country] => US
[patent_app_date] => 2022-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5792
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982314
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/982314 | Display apparatus | Nov 6, 2022 | Issued |
Array
(
[id] => 20469494
[patent_doc_number] => 12525537
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-13
[patent_title] => Transistors having backside contact structures
[patent_app_type] => utility
[patent_app_number] => 18/052558
[patent_app_country] => US
[patent_app_date] => 2022-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2096
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052558
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/052558 | Transistors having backside contact structures | Nov 2, 2022 | Issued |