Search

Adetokunbo Olusegun Torimiro

Examiner (ID: 18347, Phone: (571)270-1345 , Office: P/3714 )

Most Active Art Unit
3714
Art Unit(s)
3714, 3715
Total Applications
1106
Issued Applications
797
Pending Applications
70
Abandoned Applications
260

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20416629 [patent_doc_number] => 12499918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Sense amplifier and method thereof [patent_app_type] => utility [patent_app_number] => 18/597860 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597860
Sense Amplifier and Method Thereof Mar 5, 2024 Issued
Array ( [id] => 19038284 [patent_doc_number] => 20240088099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => 3D LAYOUT AND ORGANIZATION FOR ENHANCEMENT OF MODERN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/215681 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215681 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/215681
3D LAYOUT AND ORGANIZATION FOR ENHANCEMENT OF MODERN MEMORY SYSTEMS Jun 27, 2023 Pending
Array ( [id] => 19038284 [patent_doc_number] => 20240088099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => 3D LAYOUT AND ORGANIZATION FOR ENHANCEMENT OF MODERN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/215681 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215681 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/215681
3D LAYOUT AND ORGANIZATION FOR ENHANCEMENT OF MODERN MEMORY SYSTEMS Jun 27, 2023 Pending
Array ( [id] => 19321196 [patent_doc_number] => 20240242742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => STORAGE SYSTEM AND SEMICONDUCTOR PACKAGE WITH IMPROVED POWER SUPPLY EFFICIENCY [patent_app_type] => utility [patent_app_number] => 18/204806 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204806
STORAGE SYSTEM AND SEMICONDUCTOR PACKAGE WITH IMPROVED POWER SUPPLY EFFICIENCY May 31, 2023 Pending
Array ( [id] => 19574891 [patent_doc_number] => 20240379183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => METHOD FOR TESTING AND REPAIRING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/314825 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314825 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314825
METHOD FOR TESTING AND REPAIRING MEMORY DEVICE May 9, 2023 Pending
Array ( [id] => 17690478 [patent_doc_number] => 20220197771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => THRESHOLD VOLTAGE DISTRIBTUTION ADJUSTMENT FOR BUFFER [patent_app_type] => utility [patent_app_number] => 17/691957 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/691957
Threshold voltage distribution adjustment for buffer Mar 9, 2022 Issued
Array ( [id] => 17660457 [patent_doc_number] => 20220180922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SELECTIVE WORDLINE SCANS BASED ON A DATA STATE METRIC [patent_app_type] => utility [patent_app_number] => 17/679656 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679656
Selective wordline scans based on a data state metric Feb 23, 2022 Issued
Array ( [id] => 18508140 [patent_doc_number] => 11705972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Pooled memory system enabled by monolithic in-package optical I/O [patent_app_type] => utility [patent_app_number] => 17/583967 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 20991 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583967
Pooled memory system enabled by monolithic in-package optical I/O Jan 24, 2022 Issued
Array ( [id] => 17676346 [patent_doc_number] => 20220189513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => RECOVERY OF MEMORY FROM ASYNCHRONOUS POWER LOSS [patent_app_type] => utility [patent_app_number] => 17/561787 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561787
Recovery of memory from asynchronous power loss Dec 23, 2021 Issued
Array ( [id] => 17536455 [patent_doc_number] => 20220115064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/561545 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561545
Semiconductor memory device and memory system Dec 22, 2021 Issued
Array ( [id] => 18433240 [patent_doc_number] => 11678482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Memory array structures for capacitive sense NAND memory [patent_app_type] => utility [patent_app_number] => 17/557389 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 59 [patent_no_of_words] => 22427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557389
Memory array structures for capacitive sense NAND memory Dec 20, 2021 Issued
Array ( [id] => 17485637 [patent_doc_number] => 20220093141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/540314 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540314
Semiconductor device Dec 1, 2021 Issued
Array ( [id] => 17676354 [patent_doc_number] => 20220189521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => STORAGE CONTROLLER, STORAGE DEVICE, AND OPERATION METHOD OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/523369 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523369
Storage controller, storage device, and operation method of storage device Nov 9, 2021 Issued
Array ( [id] => 18304230 [patent_doc_number] => 11626142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/500066 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 29446 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500066
Semiconductor memory device Oct 12, 2021 Issued
Array ( [id] => 20416649 [patent_doc_number] => 12499939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Memristive logic gate circuit [patent_app_type] => utility [patent_app_number] => 18/030834 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 1545 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18030834 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/030834
MEMRISTIVE LOGIC GATE CIRCUIT Sep 27, 2021 Pending
Array ( [id] => 18195384 [patent_doc_number] => 20230048903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SIGNAL MODULATION APPARATUS, MEMORY STORAGE APPARATUS, AND SIGNAL MODULATION METHOD [patent_app_type] => utility [patent_app_number] => 17/468711 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -39 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468711
Signal modulation apparatus, memory storage apparatus, and signal modulation method Sep 7, 2021 Issued
Array ( [id] => 18415811 [patent_doc_number] => 11670356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Apparatuses and methods for refresh address masking [patent_app_type] => utility [patent_app_number] => 17/305878 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9279 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305878 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305878
Apparatuses and methods for refresh address masking Jul 15, 2021 Issued
Array ( [id] => 18415815 [patent_doc_number] => 11670360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Integrated circuit including cell array with word line assist cells [patent_app_type] => utility [patent_app_number] => 17/335606 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335606
Integrated circuit including cell array with word line assist cells May 31, 2021 Issued
Array ( [id] => 18464147 [patent_doc_number] => 11688440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Page buffer and semiconductor memory device having the same [patent_app_type] => utility [patent_app_number] => 17/220320 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 13963 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/220320
Page buffer and semiconductor memory device having the same Mar 31, 2021 Issued
16/275776 SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND WRITE METHOD Feb 13, 2019 Abandoned
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