Afsar M. Qureshi

Array ( [id] => 12573780 [patent_doc_number] => 10020186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Silicon germanium selective oxidation process [patent_app_type] => utility [patent_app_number] => 15/414500 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3470 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11824789 [patent_doc_number] => 20170213726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'Acetylide-Based Silicon Precursors And Their Use As ALD/CVD Precursors' [patent_app_type] => utility [patent_app_number] => 15/413956 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15413956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11869417 [patent_doc_number] => 20170236702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'FLUORINATION DURING ALD HIGH-K, FLUORINATION POST HIGH-K AND USE OF A POST FLUORINATION ANNEAL TO ENGINEER FLUORINE BONDING AND INCORPORATION' [patent_app_type] => utility [patent_app_number] => 15/413167 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15413167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12779575 [patent_doc_number] => 20180151693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => FinFET Device and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 15/410962 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12147570 [patent_doc_number] => 09881828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Wafer processing method' [patent_app_type] => utility [patent_app_number] => 15/410886 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 8077 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11855071 [patent_doc_number] => 20170229562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/409966 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15962 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12114948 [patent_doc_number] => 09870942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-16 [patent_title] => 'Method of forming mandrel and non-mandrel metal lines having variable widths' [patent_app_type] => utility [patent_app_number] => 15/410032 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11760449 [patent_doc_number] => 20170207318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'SCHOTTKY BARRIER STRUCTURE FOR SILICON CARBIDE (SiC) POWER DEVICES' [patent_app_type] => utility [patent_app_number] => 15/410695 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2531 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11475872 [patent_doc_number] => 20170062654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'Enhanced Light Extraction' [patent_app_type] => utility [patent_app_number] => 15/351243 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4691 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13581707 [patent_doc_number] => 20180342402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => METHOD FOR PRODUCING HIGH-PHOTOELECTRIC-CONVERSION-EFFICIENCY SOLAR CELL AND HIGH-PHOTOELECTRIC-CONVERSION-EFFICIENCY SOLAR CELL [patent_app_type] => utility [patent_app_number] => 15/755968 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15755968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11475809 [patent_doc_number] => 20170062592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'CONTACT STRUCTURE AND EXTENSION FORMATION FOR III-V NFET' [patent_app_type] => utility [patent_app_number] => 15/350065 [patent_app_country] => US [patent_app_date] => 2016-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12229928 [patent_doc_number] => 09917177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Contact structure and extension formation for III-V nFET' [patent_app_type] => utility [patent_app_number] => 15/350071 [patent_app_country] => US [patent_app_date] => 2016-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4299 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11446431 [patent_doc_number] => 20170047452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 15/335269 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5776 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11847757 [patent_doc_number] => 09735317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Method for forming a semiconducting portion by epitaxial growth on a strained portion' [patent_app_type] => utility [patent_app_number] => 15/281738 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 12601 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14332831 [patent_doc_number] => 10297442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Remote plasma based deposition of graded or multi-layered silicon carbide film [patent_app_type] => utility [patent_app_number] => 15/283159 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 15513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12615168 [patent_doc_number] => 20180096886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => COMPOSITE DIELECTRIC INTERFACE LAYERS FOR INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/282543 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12615840 [patent_doc_number] => 20180097110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/281993 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11544727 [patent_doc_number] => 20170098552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'Processed Substrate Surface For Epoxy Deposition And Method Thereof' [patent_app_type] => utility [patent_app_number] => 15/281094 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2809 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12615471 [patent_doc_number] => 20180096987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => Protection Circuit for Integrated Circuit Die-Let After Scribe Cut [patent_app_type] => utility [patent_app_number] => 15/283178 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12195523 [patent_doc_number] => 09899258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-20 [patent_title] => 'Metal liner overhang reduction and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/282440 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 7459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282440 [rel_patent_id] =>[rel_patent_doc_number] =>)