Search

Agnieszka Boesen

Examiner (ID: 9245, Phone: (571)272-8035 , Office: P/1648 )

Most Active Art Unit
1648
Art Unit(s)
1672, 1648, 1671
Total Applications
1047
Issued Applications
610
Pending Applications
117
Abandoned Applications
352

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19936991 [patent_doc_number] => 12310212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Display substrate, display panel and image display method [patent_app_type] => utility [patent_app_number] => 17/636616 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 6473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636616 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/636616
Display substrate, display panel and image display method Mar 18, 2021 Issued
Array ( [id] => 18623957 [patent_doc_number] => 11757015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/196321 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 13515 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196321
Semiconductor devices Mar 8, 2021 Issued
Array ( [id] => 17803252 [patent_doc_number] => 11417564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/190439 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4287 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190439
Semiconductor device and method for fabricating the same Mar 2, 2021 Issued
Array ( [id] => 16873659 [patent_doc_number] => 20210167126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => Multilayered Seed for Perpendicular Magnetic Structure [patent_app_type] => utility [patent_app_number] => 17/175663 [patent_app_country] => US [patent_app_date] => 2021-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175663 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175663
Multilayered seed for perpendicular magnetic structure Feb 12, 2021 Issued
Array ( [id] => 18032189 [patent_doc_number] => 11515389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/173539 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 47 [patent_no_of_words] => 9259 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173539
Semiconductor device and method for fabricating the same Feb 10, 2021 Issued
Array ( [id] => 18120573 [patent_doc_number] => 11551972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Integrated circuit devices and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/173784 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 10710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173784
Integrated circuit devices and method of manufacturing the same Feb 10, 2021 Issued
Array ( [id] => 17795832 [patent_doc_number] => 20220254924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/171760 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171760
Transistor structure and method for fabricating the same Feb 8, 2021 Issued
Array ( [id] => 18623788 [patent_doc_number] => 11756844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor device with a protection mechanism and associated systems, devices, and methods [patent_app_type] => utility [patent_app_number] => 17/170120 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 7257 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170120
Semiconductor device with a protection mechanism and associated systems, devices, and methods Feb 7, 2021 Issued
Array ( [id] => 17795806 [patent_doc_number] => 20220254898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SEMICONDUCTOR DEVICE WITH GATE SPACER AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/169911 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169911 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169911
Semiconductor device with gate spacer and manufacturing method of the semiconductor device Feb 7, 2021 Issued
Array ( [id] => 16858324 [patent_doc_number] => 20210159069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => USING SACRIFICIAL POLYMER MATERIALS IN SEMICONDUCTOR PROCESSING [patent_app_type] => utility [patent_app_number] => 17/168393 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168393
Using sacrificial polymer materials in semiconductor processing Feb 4, 2021 Issued
Array ( [id] => 17623355 [patent_doc_number] => 11342421 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Recessed access device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/167067 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6307 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167067
Recessed access device and manufacturing method thereof Feb 2, 2021 Issued
Array ( [id] => 16858386 [patent_doc_number] => 20210159131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => DIE CARRIER PACKAGE AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/165005 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165005
Die carrier package and method of forming same Feb 1, 2021 Issued
Array ( [id] => 17262738 [patent_doc_number] => 20210375723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Through-Circuit Vias in Interconnect Structures [patent_app_type] => utility [patent_app_number] => 17/162584 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162584 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162584
Through-circuit vias in interconnect structures Jan 28, 2021 Issued
Array ( [id] => 16858662 [patent_doc_number] => 20210159407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => RRAM STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/142591 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142591 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142591
RRAM structure Jan 5, 2021 Issued
Array ( [id] => 18131331 [patent_doc_number] => 11557548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Package with interlocking leads and manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/137262 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 13296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137262
Package with interlocking leads and manufacturing the same Dec 28, 2020 Issued
Array ( [id] => 17708670 [patent_doc_number] => 20220208678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => INSET POWER POST AND STRAP ARCHITECTURE WITH REDUCED VOLTAGE DROOP [patent_app_type] => utility [patent_app_number] => 17/135122 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135122
Inset power post and strap architecture with reduced voltage droop Dec 27, 2020 Issued
Array ( [id] => 18331812 [patent_doc_number] => 11637068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Thermally and electrically conductive interconnects [patent_app_type] => utility [patent_app_number] => 17/121810 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 4194 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121810
Thermally and electrically conductive interconnects Dec 14, 2020 Issued
Array ( [id] => 18857419 [patent_doc_number] => 11855014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/120825 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120825
Semiconductor device and method Dec 13, 2020 Issued
Array ( [id] => 16724058 [patent_doc_number] => 20210091205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MANUFACTURING METHOD OF AN HEMT TRANSISTOR OF THE NORMALLY OFF TYPE WITH REDUCED RESISTANCE IN THE ON STATE AND HEMT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/118439 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118439
Manufacturing method of an HEMT transistor of the normally off type with reduced resistance in the on state and HEMT transistor Dec 9, 2020 Issued
Array ( [id] => 18211952 [patent_doc_number] => 20230058216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => A SELF-ALIGNING PREPARATION METHOD FOR A DRAIN END UNDERLAP REGION OF TUNNEL FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/636980 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/636980
A SELF-ALIGNING PREPARATION METHOD FOR A DRAIN END UNDERLAP REGION OF TUNNEL FIELD EFFECT TRANSISTOR Nov 29, 2020 Abandoned
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