
Agnieszka Boesen
Examiner (ID: 9245, Phone: (571)272-8035 , Office: P/1648 )
| Most Active Art Unit | 1648 |
| Art Unit(s) | 1672, 1648, 1671 |
| Total Applications | 1047 |
| Issued Applications | 610 |
| Pending Applications | 117 |
| Abandoned Applications | 352 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17486256
[patent_doc_number] => 20220093760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE HAVING BURIED GATE ELECTRODE WITH PROTRUDING MEMBER
[patent_app_type] => utility
[patent_app_number] => 17/526125
[patent_app_country] => US
[patent_app_date] => 2021-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7602
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526125
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/526125 | Method for preparing semiconductor structure having buried gate electrode with protruding member | Nov 14, 2021 | Issued |
Array
(
[id] => 18112937
[patent_doc_number] => 20230005817
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/454877
[patent_app_country] => US
[patent_app_date] => 2021-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6660
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454877
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/454877 | Method of manufacturing a semiconductor device and a semiconductor device | Nov 14, 2021 | Issued |
Array
(
[id] => 18190836
[patent_doc_number] => 11581440
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Transistor and semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/524838
[patent_app_country] => US
[patent_app_date] => 2021-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 46
[patent_no_of_words] => 25000
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524838
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/524838 | Transistor and semiconductor device | Nov 11, 2021 | Issued |
Array
(
[id] => 17448303
[patent_doc_number] => 20220068808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-03
[patent_title] => WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/524318
[patent_app_country] => US
[patent_app_date] => 2021-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11304
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524318
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/524318 | Wiring substrate and manufacturing method thereof | Nov 10, 2021 | Issued |
Array
(
[id] => 17448202
[patent_doc_number] => 20220068707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-03
[patent_title] => PLUG & TRENCH ARCHITECTURES FOR INTEGRATED CIRCUITS & METHODS OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 17/521753
[patent_app_country] => US
[patent_app_date] => 2021-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9520
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521753
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/521753 | Plug and trench architectures for integrated circuits and methods of manufacture | Nov 7, 2021 | Issued |
Array
(
[id] => 17431691
[patent_doc_number] => 20220059400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => INTEGRATED CIRCUIT STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/520969
[patent_app_country] => US
[patent_app_date] => 2021-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6648
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520969
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/520969 | Integrated circuit structure | Nov 7, 2021 | Issued |
Array
(
[id] => 17795592
[patent_doc_number] => 20220254684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-11
[patent_title] => CONTACT STRUCTURES IN SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/519242
[patent_app_country] => US
[patent_app_date] => 2021-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519242
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/519242 | Contact structures in semiconductor devices | Nov 3, 2021 | Issued |
Array
(
[id] => 19356914
[patent_doc_number] => 12057371
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-06
[patent_title] => Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN)
[patent_app_type] => utility
[patent_app_number] => 17/511486
[patent_app_country] => US
[patent_app_date] => 2021-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 21
[patent_no_of_words] => 7458
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511486
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/511486 | Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN) | Oct 25, 2021 | Issued |
Array
(
[id] => 18840177
[patent_doc_number] => 11848256
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Semiconductor package having die pad with cooling fins
[patent_app_type] => utility
[patent_app_number] => 17/510079
[patent_app_country] => US
[patent_app_date] => 2021-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 4236
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510079
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/510079 | Semiconductor package having die pad with cooling fins | Oct 24, 2021 | Issued |
Array
(
[id] => 17551778
[patent_doc_number] => 20220123120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => Thin Film Transistor Array Substrate and Electronic Device Including the Same
[patent_app_type] => utility
[patent_app_number] => 17/505115
[patent_app_country] => US
[patent_app_date] => 2021-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16898
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505115
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/505115 | Thin film transistor array substrate and electronic device including the same | Oct 18, 2021 | Issued |
Array
(
[id] => 17417263
[patent_doc_number] => 20220052167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-17
[patent_title] => Method for Forming Source/Drain Contacts Utilizing an Inhibitor
[patent_app_type] => utility
[patent_app_number] => 17/504259
[patent_app_country] => US
[patent_app_date] => 2021-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8717
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504259
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/504259 | Method for forming source/drain contacts utilizing an inhibitor | Oct 17, 2021 | Issued |
Array
(
[id] => 17389629
[patent_doc_number] => 20220037481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-03
[patent_title] => Semiconductor Structure and its Fabricating Method
[patent_app_type] => utility
[patent_app_number] => 17/500089
[patent_app_country] => US
[patent_app_date] => 2021-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5068
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500089
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/500089 | Semiconductor structure and its fabricating method | Oct 12, 2021 | Issued |
Array
(
[id] => 19859740
[patent_doc_number] => 12262618
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Flexible display device
[patent_app_type] => utility
[patent_app_number] => 17/607507
[patent_app_country] => US
[patent_app_date] => 2021-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3441
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17607507
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/607507 | Flexible display device | Oct 11, 2021 | Issued |
Array
(
[id] => 17737961
[patent_doc_number] => 20220223423
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD AND TWO SEMICONDUCTOR STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 17/496927
[patent_app_country] => US
[patent_app_date] => 2021-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7941
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496927
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/496927 | Semiconductor structure manufacturing method and two semiconductor structures | Oct 7, 2021 | Issued |
Array
(
[id] => 17403022
[patent_doc_number] => 20220045113
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => SOLID STATE IMAGING DEVICE, MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC EQUIPMENT
[patent_app_type] => utility
[patent_app_number] => 17/496545
[patent_app_country] => US
[patent_app_date] => 2021-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15533
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496545
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/496545 | Solid state imaging device, manufacturing method of the same, and electronic equipment | Oct 6, 2021 | Issued |
Array
(
[id] => 18983546
[patent_doc_number] => 11908734
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Composite interconnect formation using graphene
[patent_app_type] => utility
[patent_app_number] => 17/450118
[patent_app_country] => US
[patent_app_date] => 2021-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5505
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450118
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/450118 | Composite interconnect formation using graphene | Oct 5, 2021 | Issued |
Array
(
[id] => 17359889
[patent_doc_number] => 20220020685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-20
[patent_title] => SLIT OXIDE AND VIA FORMATION TECHNIQUES
[patent_app_type] => utility
[patent_app_number] => 17/489262
[patent_app_country] => US
[patent_app_date] => 2021-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12989
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489262
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/489262 | Slit oxide and via formation techniques | Sep 28, 2021 | Issued |
Array
(
[id] => 17795647
[patent_doc_number] => 20220254739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-11
[patent_title] => SPECIFICATDEVICES WITH THROUGH SILICON VIAS, GUARD RINGS AND METHODS OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/481003
[patent_app_country] => US
[patent_app_date] => 2021-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8620
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481003
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/481003 | Devices with through silicon vias, guard rings and methods of making the same | Sep 20, 2021 | Issued |
Array
(
[id] => 18055791
[patent_doc_number] => 20220386877
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-08
[patent_title] => PROXIMITY-TEMPERATURE SENSOR PACKAGE AND EARPHONE APPLICATION
[patent_app_type] => utility
[patent_app_number] => 17/479210
[patent_app_country] => US
[patent_app_date] => 2021-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1448
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479210
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/479210 | PROXIMITY-TEMPERATURE SENSOR PACKAGE AND EARPHONE APPLICATION | Sep 19, 2021 | Abandoned |
Array
(
[id] => 19341574
[patent_doc_number] => 12051772
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Display device and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/447655
[patent_app_country] => US
[patent_app_date] => 2021-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 7175
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447655
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/447655 | Display device and manufacturing method thereof | Sep 13, 2021 | Issued |