Search

Ahmed N. Sefer

Examiner (ID: 7890, Phone: (571)272-1921 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893, 2826, 2821
Total Applications
1504
Issued Applications
1246
Pending Applications
13
Abandoned Applications
253

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9783147 [patent_doc_number] => 20140299967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'ELECTRONIC DEVICE STRUCTURE AND METHOD OF MAKING ELECTRONIC DEVICES AND INTEGRATED CIRCUITS USING GRAYSCALE TECHNOLOGY AND MULTILAYER THIN-FILM COMPOSITES' [patent_app_type] => utility [patent_app_number] => 13/857343 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857343 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857343
Electronic device structure and method of making electronic devices and integrated circuits using grayscale technology and multilayer thin-film composites Apr 4, 2013 Issued
Array ( [id] => 9783161 [patent_doc_number] => 20140299981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'High Power Single-Die Semiconductor Package' [patent_app_type] => utility [patent_app_number] => 13/857252 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5456 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857252 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857252
High power single-die semiconductor package Apr 4, 2013 Issued
Array ( [id] => 10898793 [patent_doc_number] => 08922015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/857247 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 12422 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857247 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857247
Semiconductor device Apr 4, 2013 Issued
Array ( [id] => 10851630 [patent_doc_number] => 08878315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Horizontal coplanar switches and methods of manufacture' [patent_app_type] => utility [patent_app_number] => 13/768235 [patent_app_country] => US [patent_app_date] => 2013-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 7467 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13768235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/768235
Horizontal coplanar switches and methods of manufacture Feb 14, 2013 Issued
Array ( [id] => 9608877 [patent_doc_number] => 08786048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/764306 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8494 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764306
Semiconductor device Feb 10, 2013 Issued
Array ( [id] => 8866093 [patent_doc_number] => 20130149796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'SEMICONDUCTOR DEVICE WITH FERRO-ELECTRIC CAPACITOR' [patent_app_type] => utility [patent_app_number] => 13/754924 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8469 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754924 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/754924
SEMICONDUCTOR DEVICE WITH FERRO-ELECTRIC CAPACITOR Jan 30, 2013 Abandoned
Array ( [id] => 9844888 [patent_doc_number] => 08946807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => '3D memory' [patent_app_type] => utility [patent_app_number] => 13/748747 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 5725 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748747 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748747
3D memory Jan 23, 2013 Issued
Array ( [id] => 9613544 [patent_doc_number] => 20140203401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'METAL-ON-METAL (MOM) CAPACITORS HAVING LATERALLY DISPLACED LAYERS, AND RELATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/748768 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6387 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748768 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748768
Metal-on-metal (MoM) capacitors having laterally displaced layers, and related systems and methods Jan 23, 2013 Issued
Array ( [id] => 10858154 [patent_doc_number] => 08884358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Method of making a non-volatile memory (NVM) cell structure' [patent_app_type] => utility [patent_app_number] => 13/748808 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3557 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748808
Method of making a non-volatile memory (NVM) cell structure Jan 23, 2013 Issued
Array ( [id] => 9589938 [patent_doc_number] => 08779481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'SOI-based CMOS imagers employing flash gate/chemisorption processing' [patent_app_type] => utility [patent_app_number] => 13/749427 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 33 [patent_no_of_words] => 8792 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13749427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/749427
SOI-based CMOS imagers employing flash gate/chemisorption processing Jan 23, 2013 Issued
Array ( [id] => 9613576 [patent_doc_number] => 20140203433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'IN-SITU THERMOELECTRIC COOLING' [patent_app_type] => utility [patent_app_number] => 13/748821 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5072 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748821 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748821
In-situ thermoelectric cooling Jan 23, 2013 Issued
Array ( [id] => 9565948 [patent_doc_number] => 20140183661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'FinFET Device Structure and Methods of Making Same' [patent_app_type] => utility [patent_app_number] => 13/748312 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6153 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748312 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748312
FinFET device structure and methods of making same Jan 22, 2013 Issued
Array ( [id] => 9613599 [patent_doc_number] => 20140203456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'Pre-Applying Supporting Materials between Bonded Package Components' [patent_app_type] => utility [patent_app_number] => 13/748351 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748351 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748351
Pre-applying supporting materials between bonded package components Jan 22, 2013 Issued
Array ( [id] => 8947800 [patent_doc_number] => 20130193580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/748255 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4218 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748255 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748255
Method of manufacturing semiconductor device and semiconductor device Jan 22, 2013 Issued
Array ( [id] => 9613543 [patent_doc_number] => 20140203400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'METAL-INSULATOR-METAL CAPACITOR FORMATION TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 13/748277 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10875 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748277 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748277
Metal-insulator-metal capacitor formation techniques Jan 22, 2013 Issued
Array ( [id] => 9303915 [patent_doc_number] => 20140042589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/748218 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748218 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748218
Semiconductor device Jan 22, 2013 Issued
Array ( [id] => 11453370 [patent_doc_number] => 09577022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Inductor' [patent_app_type] => utility [patent_app_number] => 13/746366 [patent_app_country] => US [patent_app_date] => 2013-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4393 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746366 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/746366
Inductor Jan 21, 2013 Issued
Array ( [id] => 9613591 [patent_doc_number] => 20140203448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'RANDOM CODED INTEGRATED CIRCUIT STRUCTURES AND METHODS OF MAKING RANDOM CODED INTEGRATED CIRCUIT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/746427 [patent_app_country] => US [patent_app_date] => 2013-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/746427
Random coded integrated circuit structures and methods of making random coded integrated circuit structures Jan 21, 2013 Issued
Array ( [id] => 9613553 [patent_doc_number] => 20140203410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS' [patent_app_type] => utility [patent_app_number] => 13/747094 [patent_app_country] => US [patent_app_date] => 2013-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6889 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13747094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/747094
Die edge sealing structures and related fabrication methods Jan 21, 2013 Issued
Array ( [id] => 10893340 [patent_doc_number] => 08916955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'Nearly buffer zone free layout methodology' [patent_app_type] => utility [patent_app_number] => 13/745913 [patent_app_country] => US [patent_app_date] => 2013-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13745913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/745913
Nearly buffer zone free layout methodology Jan 20, 2013 Issued
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