Search

Aimee J. Li

Supervisory Patent Examiner (ID: 12544, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2195, 2137, 2100
Total Applications
539
Issued Applications
378
Pending Applications
20
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 146737 [patent_doc_number] => 07694111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system' [patent_app_type] => utility [patent_app_number] => 12/033785 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 8352 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694111.pdf [firstpage_image] =>[orig_patent_app_number] => 12033785 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033785
Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system Feb 18, 2008 Issued
Array ( [id] => 4868950 [patent_doc_number] => 20080148009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS AND COMMUNICATION ELEMENTS' [patent_app_type] => utility [patent_app_number] => 12/028565 [patent_app_country] => US [patent_app_date] => 2008-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21081 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148009.pdf [firstpage_image] =>[orig_patent_app_number] => 12028565 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/028565
Processing system with interspersed processors and communication elements Feb 7, 2008 Issued
Array ( [id] => 8580837 [patent_doc_number] => 08347067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Instruction pre-decoding of multiple instruction sets' [patent_app_type] => utility [patent_app_number] => 12/010312 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 34 [patent_no_of_words] => 15248 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12010312 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010312
Instruction pre-decoding of multiple instruction sets Jan 22, 2008 Issued
Array ( [id] => 4678022 [patent_doc_number] => 20080215653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Data Processing Device with Multi-Endian Support' [patent_app_type] => utility [patent_app_number] => 11/962658 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2843 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20080215653.pdf [firstpage_image] =>[orig_patent_app_number] => 11962658 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962658
Data Processing Device with Multi-Endian Support Dec 20, 2007 Abandoned
Array ( [id] => 4787675 [patent_doc_number] => 20080141004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Apparatus and method for performing re-arrangement operations on data' [patent_app_type] => utility [patent_app_number] => 11/987720 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9468 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141004.pdf [firstpage_image] =>[orig_patent_app_number] => 11987720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987720
Apparatus and method for performing re-arrangement operations on data Dec 3, 2007 Issued
Array ( [id] => 4923704 [patent_doc_number] => 20080072021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Floating point exception handling in a risc microprocessor architecture' [patent_app_type] => utility [patent_app_number] => 11/981453 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 47839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072021.pdf [firstpage_image] =>[orig_patent_app_number] => 11981453 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981453
Floating point exception handling in a risc microprocessor architecture Oct 30, 2007 Abandoned
Array ( [id] => 4923674 [patent_doc_number] => 20080071991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Using trap routines in a RISC microprocessor architecture' [patent_app_type] => utility [patent_app_number] => 11/981482 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 47821 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20080071991.pdf [firstpage_image] =>[orig_patent_app_number] => 11981482 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981482
Using trap routines in a RISC microprocessor architecture Oct 30, 2007 Abandoned
Array ( [id] => 4747318 [patent_doc_number] => 20080091920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Transferring data between registers in a RISC microprocessor architecture' [patent_app_type] => utility [patent_app_number] => 11/981237 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 47777 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091920.pdf [firstpage_image] =>[orig_patent_app_number] => 11981237 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981237
Transferring data between registers in a RISC microprocessor architecture Oct 30, 2007 Abandoned
Array ( [id] => 4940591 [patent_doc_number] => 20080077911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Using breakpoints for debugging in a RISC microprocessor architecture' [patent_app_type] => utility [patent_app_number] => 11/981278 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 47891 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20080077911.pdf [firstpage_image] =>[orig_patent_app_number] => 11981278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981278
Using breakpoints for debugging in a RISC microprocessor architecture Oct 30, 2007 Abandoned
Array ( [id] => 4945473 [patent_doc_number] => 20080082800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Data processor for modifying and executing operation of instruction code' [patent_app_type] => utility [patent_app_number] => 11/976568 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 16476 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082800.pdf [firstpage_image] =>[orig_patent_app_number] => 11976568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976568
Data processor for modifying and executing operation of instruction code Oct 24, 2007 Abandoned
Array ( [id] => 4766769 [patent_doc_number] => 20080177981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'APPARATUS AND METHOD FOR DECREASING THE LATENCY BETWEEN INSTRUCTION CACHE AND A PIPELINE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/868557 [patent_app_country] => US [patent_app_date] => 2007-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3993 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20080177981.pdf [firstpage_image] =>[orig_patent_app_number] => 11868557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/868557
Apparatus and method for decreasing the latency between instruction cache and a pipeline processor Oct 7, 2007 Issued
Array ( [id] => 7726303 [patent_doc_number] => 08099583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing' [patent_app_type] => utility [patent_app_number] => 11/973184 [patent_app_country] => US [patent_app_date] => 2007-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3923 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099583.pdf [firstpage_image] =>[orig_patent_app_number] => 11973184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/973184
Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing Oct 5, 2007 Issued
Array ( [id] => 4693855 [patent_doc_number] => 20080086626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Inter-processor communication method' [patent_app_type] => utility [patent_app_number] => 11/973173 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7135 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086626.pdf [firstpage_image] =>[orig_patent_app_number] => 11973173 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/973173
Inter-processor communication method Oct 4, 2007 Issued
Array ( [id] => 107730 [patent_doc_number] => 07725696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-25 [patent_title] => 'Method and apparatus for modulo scheduled loop execution in a processor architecture' [patent_app_type] => utility [patent_app_number] => 11/867127 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 9103 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725696.pdf [firstpage_image] =>[orig_patent_app_number] => 11867127 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867127
Method and apparatus for modulo scheduled loop execution in a processor architecture Oct 3, 2007 Issued
Array ( [id] => 5273570 [patent_doc_number] => 20090077346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'PROCESSING MODULE, PROCESSOR CIRCUIT, INSTRUCTION SET FOR PROCESSING DATA, AND METHOD FOR SYNCHRONIZING THE PROCESSING OF CODES' [patent_app_type] => utility [patent_app_number] => 11/855383 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8453 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077346.pdf [firstpage_image] =>[orig_patent_app_number] => 11855383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855383
Processing module, processor circuit, instruction set for processing data, and method for synchronizing the processing of codes Sep 13, 2007 Issued
Array ( [id] => 5339168 [patent_doc_number] => 20090055632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Emulation Scheme for Programmable Pipeline Fabric' [patent_app_type] => utility [patent_app_number] => 11/843596 [patent_app_country] => US [patent_app_date] => 2007-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055632.pdf [firstpage_image] =>[orig_patent_app_number] => 11843596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/843596
Emulation Scheme for Programmable Pipeline Fabric Aug 21, 2007 Abandoned
Array ( [id] => 8158161 [patent_doc_number] => 08171264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Control sub-unit and control main unit' [patent_app_type] => utility [patent_app_number] => 11/843295 [patent_app_country] => US [patent_app_date] => 2007-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 12419 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171264.pdf [firstpage_image] =>[orig_patent_app_number] => 11843295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/843295
Control sub-unit and control main unit Aug 21, 2007 Issued
Array ( [id] => 5339172 [patent_doc_number] => 20090055636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'METHOD FOR GENERATING AND APPLYING A MODEL TO PREDICT HARDWARE PERFORMANCE HAZARDS IN A MACHINE INSTRUCTION SEQUENCE' [patent_app_type] => utility [patent_app_number] => 11/843386 [patent_app_country] => US [patent_app_date] => 2007-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055636.pdf [firstpage_image] =>[orig_patent_app_number] => 11843386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/843386
METHOD FOR GENERATING AND APPLYING A MODEL TO PREDICT HARDWARE PERFORMANCE HAZARDS IN A MACHINE INSTRUCTION SEQUENCE Aug 21, 2007 Abandoned
Array ( [id] => 5339164 [patent_doc_number] => 20090055628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'METHODS AND COMPUTER PROGRAM PRODUCTS FOR REDUCING LOAD-HIT-STORE DELAYS BY ASSIGNING MEMORY FETCH UNITS TO CANDIDATE VARIABLES' [patent_app_type] => utility [patent_app_number] => 11/842289 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2571 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055628.pdf [firstpage_image] =>[orig_patent_app_number] => 11842289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842289
METHODS AND COMPUTER PROGRAM PRODUCTS FOR REDUCING LOAD-HIT-STORE DELAYS BY ASSIGNING MEMORY FETCH UNITS TO CANDIDATE VARIABLES Aug 20, 2007 Abandoned
Array ( [id] => 4735515 [patent_doc_number] => 20080052497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 11/840116 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 26224 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052497.pdf [firstpage_image] =>[orig_patent_app_number] => 11840116 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840116
Parallel operation device allowing efficient parallel operational processing Aug 15, 2007 Issued
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