Search

Aimee J. Li

Examiner (ID: 2492)

Most Active Art Unit
2183
Art Unit(s)
2195, 2137, 2183, 2100
Total Applications
539
Issued Applications
378
Pending Applications
21
Abandoned Applications
140

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 58115 [patent_doc_number] => 07774581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same' [patent_app_type] => utility [patent_app_number] => 11/838511 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5068 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774581.pdf [firstpage_image] =>[orig_patent_app_number] => 11838511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838511
Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same Aug 13, 2007 Issued
Array ( [id] => 8804891 [patent_doc_number] => 08443174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Processor and method of performing speculative load operations of the processor' [patent_app_type] => utility [patent_app_number] => 11/838488 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3783 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11838488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838488
Processor and method of performing speculative load operations of the processor Aug 13, 2007 Issued
Array ( [id] => 5448060 [patent_doc_number] => 20090049286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING IMPROVED BRANCH TARGET ADDRESS CACHE' [patent_app_type] => utility [patent_app_number] => 11/837893 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6203 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20090049286.pdf [firstpage_image] =>[orig_patent_app_number] => 11837893 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/837893
Branch target address cache Aug 12, 2007 Issued
Array ( [id] => 4641944 [patent_doc_number] => 08019978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-13 [patent_title] => 'Unit status reporting protocol' [patent_app_type] => utility [patent_app_number] => 11/837933 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019978.pdf [firstpage_image] =>[orig_patent_app_number] => 11837933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/837933
Unit status reporting protocol Aug 12, 2007 Issued
Array ( [id] => 4486528 [patent_doc_number] => 07870372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Interrupt handling' [patent_app_type] => utility [patent_app_number] => 11/838075 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5485 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870372.pdf [firstpage_image] =>[orig_patent_app_number] => 11838075 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838075
Interrupt handling Aug 12, 2007 Issued
Array ( [id] => 4653322 [patent_doc_number] => 20080040579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'METHODS AND APPARATUS FOR HANDLING SWITCHING AMONG THREADS WITHIN A MULTITHREAD PROCESSOR' [patent_app_type] => utility [patent_app_number] => 11/836044 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6264 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040579.pdf [firstpage_image] =>[orig_patent_app_number] => 11836044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/836044
Methods and apparatus for handling switching among threads within a multithread processor Aug 7, 2007 Issued
Array ( [id] => 4671625 [patent_doc_number] => 20080046686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Method and Apparatus for an Inductive Doubling Architecture' [patent_app_type] => utility [patent_app_number] => 11/834333 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 39057 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046686.pdf [firstpage_image] =>[orig_patent_app_number] => 11834333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/834333
Method and apparatus for an inductive doubling architecture Aug 5, 2007 Issued
Array ( [id] => 4498836 [patent_doc_number] => 07886133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Information processing apparatus and method for accelerating information processing' [patent_app_type] => utility [patent_app_number] => 11/833275 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7825 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886133.pdf [firstpage_image] =>[orig_patent_app_number] => 11833275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833275
Information processing apparatus and method for accelerating information processing Aug 2, 2007 Issued
Array ( [id] => 4602833 [patent_doc_number] => 07979677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor' [patent_app_type] => utility [patent_app_number] => 11/833561 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2199 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979677.pdf [firstpage_image] =>[orig_patent_app_number] => 11833561 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833561
Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor Aug 2, 2007 Issued
Array ( [id] => 4653467 [patent_doc_number] => 20080040724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'INSTRUCTION DISPATCHING METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/833099 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5524 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040724.pdf [firstpage_image] =>[orig_patent_app_number] => 11833099 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833099
Instruction dispatching method and apparatus Aug 1, 2007 Issued
Array ( [id] => 4498829 [patent_doc_number] => 07886131 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-08 [patent_title] => 'Multithread processor with thread based throttling' [patent_app_type] => utility [patent_app_number] => 11/833127 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4444 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886131.pdf [firstpage_image] =>[orig_patent_app_number] => 11833127 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833127
Multithread processor with thread based throttling Aug 1, 2007 Issued
Array ( [id] => 163315 [patent_doc_number] => 07676654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Extended register space apparatus and methods for processors' [patent_app_type] => utility [patent_app_number] => 11/830473 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5264 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676654.pdf [firstpage_image] =>[orig_patent_app_number] => 11830473 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830473
Extended register space apparatus and methods for processors Jul 29, 2007 Issued
Array ( [id] => 5029994 [patent_doc_number] => 20070271441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Availability of space in a RISC microprocessor architecture' [patent_app_type] => utility [patent_app_number] => 11/881283 [patent_app_country] => US [patent_app_date] => 2007-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 47875 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271441.pdf [firstpage_image] =>[orig_patent_app_number] => 11881283 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/881283
Availability of space in a RISC microprocessor architecture Jul 25, 2007 Abandoned
Array ( [id] => 5029995 [patent_doc_number] => 20070271442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Detecting the boundaries of memory in a RISC microprocessor architecture' [patent_app_type] => utility [patent_app_number] => 11/881284 [patent_app_country] => US [patent_app_date] => 2007-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 47946 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271442.pdf [firstpage_image] =>[orig_patent_app_number] => 11881284 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/881284
Detecting the boundaries of memory in a RISC microprocessor architecture Jul 25, 2007 Abandoned
Array ( [id] => 4454974 [patent_doc_number] => 07966479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-21 [patent_title] => 'Concurrent vs. low power branch prediction' [patent_app_type] => utility [patent_app_number] => 11/880859 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 21965 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966479.pdf [firstpage_image] =>[orig_patent_app_number] => 11880859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/880859
Concurrent vs. low power branch prediction Jul 22, 2007 Issued
Array ( [id] => 5311984 [patent_doc_number] => 20090019265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'ADAPTIVE EXECUTION FREQUENCY CONTROL METHOD FOR ENHANCED INSTRUCTION THROUGHPUT' [patent_app_type] => utility [patent_app_number] => 11/776222 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019265.pdf [firstpage_image] =>[orig_patent_app_number] => 11776222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/776222
Adaptive execution frequency control method for enhanced instruction throughput Jul 10, 2007 Issued
Array ( [id] => 237694 [patent_doc_number] => 07596683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Switching processor threads during long latencies' [patent_app_type] => utility [patent_app_number] => 11/827207 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2707 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596683.pdf [firstpage_image] =>[orig_patent_app_number] => 11827207 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/827207
Switching processor threads during long latencies Jul 10, 2007 Issued
Array ( [id] => 5311983 [patent_doc_number] => 20090019264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'ADAPTIVE EXECUTION CYCLE CONTROL METHOD FOR ENHANCED INSTRUCTION THROUGHPUT' [patent_app_type] => utility [patent_app_number] => 11/776121 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019264.pdf [firstpage_image] =>[orig_patent_app_number] => 11776121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/776121
Adaptive execution cycle control method for enhanced instruction throughput Jul 10, 2007 Issued
Array ( [id] => 4499614 [patent_doc_number] => 07904703 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'Method and apparatus for idling and waking threads by a multithread processor' [patent_app_type] => utility [patent_app_number] => 11/775661 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5576 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904703.pdf [firstpage_image] =>[orig_patent_app_number] => 11775661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775661
Method and apparatus for idling and waking threads by a multithread processor Jul 9, 2007 Issued
Array ( [id] => 5311976 [patent_doc_number] => 20090019257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Method and Apparatus for Length Decoding and Identifying Boundaries of Variable Length Instructions' [patent_app_type] => utility [patent_app_number] => 11/775456 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019257.pdf [firstpage_image] =>[orig_patent_app_number] => 11775456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775456
Method and apparatus for length decoding and identifying boundaries of variable length instructions Jul 9, 2007 Issued
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