
Aimee J. Li
Examiner (ID: 2492)
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2195, 2137, 2183, 2100 |
| Total Applications | 539 |
| Issued Applications | 378 |
| Pending Applications | 21 |
| Abandoned Applications | 140 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 58115
[patent_doc_number] => 07774581
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[patent_title] => 'Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same'
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[patent_app_number] => 11/838511
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/838511 | Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same | Aug 13, 2007 | Issued |
Array
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[patent_issue_date] => 2013-05-14
[patent_title] => 'Processor and method of performing speculative load operations of the processor'
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[patent_app_date] => 2007-08-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/838488 | Processor and method of performing speculative load operations of the processor | Aug 13, 2007 | Issued |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING IMPROVED BRANCH TARGET ADDRESS CACHE'
[patent_app_type] => utility
[patent_app_number] => 11/837893
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[patent_app_date] => 2007-08-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/837893 | Branch target address cache | Aug 12, 2007 | Issued |
Array
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[patent_issue_date] => 2011-09-13
[patent_title] => 'Unit status reporting protocol'
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[patent_app_date] => 2007-08-13
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Array
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[patent_title] => 'Interrupt handling'
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[patent_app_date] => 2007-08-13
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Array
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[patent_title] => 'METHODS AND APPARATUS FOR HANDLING SWITCHING AMONG THREADS WITHIN A MULTITHREAD PROCESSOR'
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Array
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[patent_title] => 'Method and Apparatus for an Inductive Doubling Architecture'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/834333 | Method and apparatus for an inductive doubling architecture | Aug 5, 2007 | Issued |
Array
(
[id] => 4498836
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[patent_title] => 'Information processing apparatus and method for accelerating information processing'
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Array
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[id] => 4602833
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[patent_title] => 'Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor'
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Array
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[patent_title] => 'INSTRUCTION DISPATCHING METHOD AND APPARATUS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/833099 | Instruction dispatching method and apparatus | Aug 1, 2007 | Issued |
Array
(
[id] => 4498829
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[patent_title] => 'Multithread processor with thread based throttling'
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Array
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[patent_title] => 'Extended register space apparatus and methods for processors'
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Array
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Array
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Array
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Array
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Array
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