
Aimee J. Li
Supervisory Patent Examiner (ID: 5820, Phone: (571)272-4169 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2100, 2137, 2195 |
| Total Applications | 539 |
| Issued Applications | 378 |
| Pending Applications | 21 |
| Abandoned Applications | 140 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8779
[patent_doc_number] => 07818542
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[patent_kind] => B2
[patent_issue_date] => 2010-10-19
[patent_title] => 'Method and apparatus for length decoding variable length instructions'
[patent_app_type] => utility
[patent_app_number] => 11/775451
[patent_app_country] => US
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Array
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[patent_issue_date] => 2010-07-13
[patent_title] => 'Methods, apparatuses, and system for facilitating control of multiple instruction threads'
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Array
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[patent_title] => 'Store queue architecture for a processor that supports speculative execution'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/774705 | Store queue architecture for a processor that supports speculative execution | Jul 8, 2007 | Issued |
Array
(
[id] => 4754799
[patent_doc_number] => 20080162875
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[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Parallel Data Processing Apparatus'
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Array
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[patent_doc_number] => 07613912
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[patent_title] => 'System and method for simulating hardware interrupts'
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Array
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Array
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Array
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[patent_title] => 'Method and apparatus for employing multi-bit register file cells and SMT thread groups'
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[patent_app_number] => 11/762137
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Array
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[id] => 87661
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[patent_title] => 'Processor having a dedicated hash unit integrated within'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/758892 | Processor having a dedicated hash unit integrated within | Jun 5, 2007 | Issued |
Array
(
[id] => 188582
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/758515 | Non-temporal memory reference control mechanism | Jun 4, 2007 | Issued |
Array
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[id] => 188581
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Array
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Array
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Array
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Array
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Array
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Array
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[patent_title] => 'FAST SPARSE LIST WALKER'
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