Search

Aimee J. Li

Supervisory Patent Examiner (ID: 5820, Phone: (571)272-4169 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2100, 2137, 2195
Total Applications
539
Issued Applications
378
Pending Applications
21
Abandoned Applications
140

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8779 [patent_doc_number] => 07818542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Method and apparatus for length decoding variable length instructions' [patent_app_type] => utility [patent_app_number] => 11/775451 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818542.pdf [firstpage_image] =>[orig_patent_app_number] => 11775451 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775451
Method and apparatus for length decoding variable length instructions Jul 9, 2007 Issued
Array ( [id] => 76404 [patent_doc_number] => 07757070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-13 [patent_title] => 'Methods, apparatuses, and system for facilitating control of multiple instruction threads' [patent_app_type] => utility [patent_app_number] => 11/775444 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5828 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/757/07757070.pdf [firstpage_image] =>[orig_patent_app_number] => 11775444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775444
Methods, apparatuses, and system for facilitating control of multiple instruction threads Jul 9, 2007 Issued
Array ( [id] => 4586487 [patent_doc_number] => 07849290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Store queue architecture for a processor that supports speculative execution' [patent_app_type] => utility [patent_app_number] => 11/774705 [patent_app_country] => US [patent_app_date] => 2007-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5405 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849290.pdf [firstpage_image] =>[orig_patent_app_number] => 11774705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774705
Store queue architecture for a processor that supports speculative execution Jul 8, 2007 Issued
Array ( [id] => 4754799 [patent_doc_number] => 20080162875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Parallel Data Processing Apparatus' [patent_app_type] => utility [patent_app_number] => 11/774500 [patent_app_country] => US [patent_app_date] => 2007-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12767 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162875.pdf [firstpage_image] =>[orig_patent_app_number] => 11774500 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774500
Parallel Data Processing Apparatus Jul 5, 2007 Abandoned
Array ( [id] => 220378 [patent_doc_number] => 07613912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'System and method for simulating hardware interrupts' [patent_app_type] => utility [patent_app_number] => 11/771688 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613912.pdf [firstpage_image] =>[orig_patent_app_number] => 11771688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771688
System and method for simulating hardware interrupts Jun 28, 2007 Issued
Array ( [id] => 4690005 [patent_doc_number] => 20080034186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/772079 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12770 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034186.pdf [firstpage_image] =>[orig_patent_app_number] => 11772079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772079
Parallel data processing apparatus Jun 28, 2007 Issued
Array ( [id] => 4690004 [patent_doc_number] => 20080034185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/772037 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12769 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034185.pdf [firstpage_image] =>[orig_patent_app_number] => 11772037 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772037
Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions Jun 28, 2007 Issued
Array ( [id] => 9665816 [patent_doc_number] => 08812824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Method and apparatus for employing multi-bit register file cells and SMT thread groups' [patent_app_type] => utility [patent_app_number] => 11/762137 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 10123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11762137 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/762137
Method and apparatus for employing multi-bit register file cells and SMT thread groups Jun 12, 2007 Issued
Array ( [id] => 87661 [patent_doc_number] => 07743235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Processor having a dedicated hash unit integrated within' [patent_app_type] => utility [patent_app_number] => 11/758892 [patent_app_country] => US [patent_app_date] => 2007-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 11137 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743235.pdf [firstpage_image] =>[orig_patent_app_number] => 11758892 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758892
Processor having a dedicated hash unit integrated within Jun 5, 2007 Issued
Array ( [id] => 188582 [patent_doc_number] => 07647479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Non-temporal memory reference control mechanism' [patent_app_type] => utility [patent_app_number] => 11/758515 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8987 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647479.pdf [firstpage_image] =>[orig_patent_app_number] => 11758515 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758515
Non-temporal memory reference control mechanism Jun 4, 2007 Issued
Array ( [id] => 188581 [patent_doc_number] => 07647478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Suppression of store checking' [patent_app_type] => utility [patent_app_number] => 11/758504 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9275 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647478.pdf [firstpage_image] =>[orig_patent_app_number] => 11758504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758504
Suppression of store checking Jun 4, 2007 Issued
Array ( [id] => 8777 [patent_doc_number] => 07818541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Data processing architectures' [patent_app_type] => utility [patent_app_number] => 11/752299 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 17125 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818541.pdf [firstpage_image] =>[orig_patent_app_number] => 11752299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/752299
Data processing architectures May 22, 2007 Issued
Array ( [id] => 4826445 [patent_doc_number] => 20080229311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Interface processor' [patent_app_type] => utility [patent_app_number] => 11/717622 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11009 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229311.pdf [firstpage_image] =>[orig_patent_app_number] => 11717622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717622
Interface processor Mar 13, 2007 Issued
Array ( [id] => 8552224 [patent_doc_number] => 08327122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Method and system for providing context switch using multiple register file' [patent_app_type] => utility [patent_app_number] => 11/712998 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3766 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11712998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/712998
Method and system for providing context switch using multiple register file Mar 1, 2007 Issued
Array ( [id] => 7588920 [patent_doc_number] => 07664937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Self-checking code for tamper-resistance based on code overlapping' [patent_app_type] => utility [patent_app_number] => 11/681160 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/664/07664937.pdf [firstpage_image] =>[orig_patent_app_number] => 11681160 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/681160
Self-checking code for tamper-resistance based on code overlapping Feb 28, 2007 Issued
Array ( [id] => 4730452 [patent_doc_number] => 20080209173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Branch predictor directed prefetch' [patent_app_type] => utility [patent_app_number] => 11/711925 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209173.pdf [firstpage_image] =>[orig_patent_app_number] => 11711925 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711925
Branch predictor directed prefetch Feb 27, 2007 Issued
Array ( [id] => 4730471 [patent_doc_number] => 20080209183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'FAST SPARSE LIST WALKER' [patent_app_type] => utility [patent_app_number] => 11/679282 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209183.pdf [firstpage_image] =>[orig_patent_app_number] => 11679282 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679282
Fast sparse list walker Feb 26, 2007 Issued
Array ( [id] => 96883 [patent_doc_number] => 07734899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Reducing data hazards in pipelined processors to provide high processor utilization' [patent_app_type] => utility [patent_app_number] => 11/711288 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7794 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/734/07734899.pdf [firstpage_image] =>[orig_patent_app_number] => 11711288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711288
Reducing data hazards in pipelined processors to provide high processor utilization Feb 25, 2007 Issued
Array ( [id] => 5179380 [patent_doc_number] => 20070180440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Methods and Apparatus for Meta-Architecture Defined Programmable Instruction Fetch Functions Supporting Assembled Variable Length Instruction Processors' [patent_app_type] => utility [patent_app_number] => 11/677640 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20070180440.pdf [firstpage_image] =>[orig_patent_app_number] => 11677640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677640
Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors Feb 21, 2007 Issued
Array ( [id] => 7589509 [patent_doc_number] => 07664934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Data processor decoding instruction formats using operand data' [patent_app_type] => utility [patent_app_number] => 11/706333 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 17473 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/664/07664934.pdf [firstpage_image] =>[orig_patent_app_number] => 11706333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706333
Data processor decoding instruction formats using operand data Feb 14, 2007 Issued
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